International Business Machines Corporation

Marc Alan Auslander

Peter W Markstein

Robert William Wisniewski

Orran Yaakov Krieger

Kemal Ebcioglu

John Cocke

Kartik Agaram

Hubertus Franke

Bryan Savoye Rosenburg

Albert Y Chang

George Radin

Hsieh T Hao

David Joel Edelsohn

Stephen P Morgan

Larry Wayne Loen

John Thomas O'Quin, Ii

Dilma Menezes Da Silva

Martin Edward Hopkins

John C O'Quin, Iii

Tracy Jay Kimbrel

Jochen Liedtke

Jonathan Appavoo

Robert Morris Meade

Kevin Kin-Fai Hui

Systems, especially operating systems, are becoming more complex to the point where maintaining them by humans is becoming nearly impossible. Many corporations have recognized this trend and have begun investing in autonomic technology. Autonomic technology allows a piece of software to monitor, diagnose, and repair itself. This can be used for improved performance, reliability, maintainability, security, etc. Disclosed herein is a mechanism to allow operating systems to hot swap a piece of operating system code, while continuing to offer to the user the service which that code is providing. This can be used, for examples, to increase the performance of an application or to fix a detected security hole live without bringing the machine down. Some autonomic ability will be mandatory in next generation operating system for without it they will collapse under their own complexity. The invention offers a key component of being able to achieve autonomic computing.

Achieving autonomic behavior in an operating system via a hot-swapping mechanism

Methods and arrangements for accessing a storage structure. Included are an arrangement for providing a storage access instruction, an arrangement for inputting an address into a storage structure data cache responsive to a storage access instruction, an arrangement for extending a storage access instruction with a predicted register number field, the predicted register number field containing a predicted register number corresponding to a speculative location of a load/store operand associated with a storage access instruction, an arrangement for speculatively accessing a storage structure with a storage access instruction extended by the extending arrangement, and an arrangement for reverting to the arrangement for inputting an address if the load/store operand is not in the speculative location.

Runtime register allocator

A method and apparatus for performing efficient interprocess communication (IPC) in a computer system. With this invention, a memory region called the IPC transfer region is shared among all processes of the system to enable more efficient IPC. The unique physical address of the region is mapped into a virtual address from each of the address spaces of the processes of the system. When one of the processes needs to transfer data to another of the processes, the first process stores arguments describing the data in the region using the virtual address in its address space that maps into the unique physical address. When the other or second process needs to receive the data, the second process reads the data from the second region using the virtual address in its memory space that maps into the unique physical address. With this invention, in most cases, control of the IPC transfer region occurs automatically without any kernel intervention.

Technique for efficiently transferring moderate amounts of data across address space boundary

In a computer system, a method and apparatus for scheduling activities' access to a resource with minimal involvement of the kernel of the operating system. More specifically, a &ldquo;next bid&rdquo; is maintained, and this parameter identifies the highest bid for the resource by any activity not currently accessing the resource. The accessing activity then compares its bid, which can be time varying, with the &ldquo;next bid&rdquo; to determine whether it should release the resource to another activity. The &ldquo;next bid&rdquo; can be accessed without any system calls to the operating system. This allows the activity to determine whether to relinquish control to the system without the necessity of communication between the two. Likewise, the operating system can access the bid of the accessing activity without explicit communication. This allows the system to determine whether to preempt the accessing activity without the necessity of communication between the two.

Locally made, globally coordinated resource allocation decisions based on information provided by the second-price auction model

There is provided a method for representing unvalues in an unvalue-unaware memory of a computer processing system. The method includes the step of selecting arbitrary bit combinations to represent the unvalues, upon startup of the system. Upon performing a read operation from the memory, a read value is interpreted as an unvalue, when the read value matches at least one of the bit combinations. Upon performing a write operation to the memory, a value-unvalue-collision exception is raised, when a valid value is written to the memory and the valid value matches at least one of the bit combinations.

Unvalue-tagged memory without additional bits

A conventional bi-endian computer system is enhanced to include mixed-endian mechanisms that allows the computer system to dynamically change its endian mode. The mixed-endian computer system can change endian mode on a task by task basis if necessary. The mixed-endian mechanisms automatically format the data in the form expected by the running task, regardless of whether the task expects the data to be in big endian format or in little endian format. The mixed-endian mechanisms also format big and little endian instructions such that they can execute on the same computer system. The mixed-endian mechanisms also include two memory management mechanisms, a single aliased memory management mechanism and a double aliased memory management mechanism. Each memory management mechanism provides cross-endian data sharing.

Mixed-endian computer system that provides cross-endian data sharing

A first group of memory locations stores information. The first group is arranged into multiple congruence classes of memory locations. The congruence classes include a first congruence class having more than one memory location. A second group of memory locations stores information from the first group of memory locations. Directory locations store information relating the first and second groups of memory locations. The directory locations include a first directory location able to store information relating a particular one of the second group of memory locations to any memory location of more than one of the congruence classes including the first congruence class.

Circuitry and method for relating first and second memory locations

A data processing method for storing groups of related information in a storage subsystem of a data processing system in which the storage subsystem includes one or more storage devices having a plurality of block addressable storage locations (blocks or sectors) each of which stores a predetermined fixed number of bytes of said information. The method includes the step of establishing allocatable increments of storage, called physical partitions, which comprise a predetermined number of contiguous addressable blocks, and initially allocating, in response to a request to the operating system, a preselected number of partitions for each group of related information, where the partitions in each group are not necessarily physically contiguous and where the number that is selected is the minimum number of partitions required to store the group of related information. The method further includes the step of automatically allocating one or more additional partitions, located physically on any device, to a previously allocated group of related partitions, dynamically in response to another request of the operating system. A group of partitions that have been allocated to store a group of related information, such as individual files that are related in a hierarchical file system, is called a 'Logical Volume'. Logical Volumes may be further combined for administration and data management reasons into a 'Volume Group'.

Data processing method to create virtual disks from non-contiguous

A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises: Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the 'kill set' for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and 'kill set' information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.

Method for improving global common subexpression elimination and code

A method operable within an optimizing compiler for generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element 'n' in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element 'n' appears. The symbolic register assigned to the tuple in the table is chosen to total the result of the computation of the non-basis element; and finally, a second table is constructed so that given a symbolic register, the computation which it represents can be retrieved.

Method of developing formal identities and program bases in an

A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

Condition register architecture for a primitive instruction set machine

A mechanism for performing a run-time storage address validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

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Millwood, NY, United States of America

Marc Alan Auslander