Altera Corporation

Lsi Logic Corporation

Tabula, Inc.

Marc A Miller

Steven L Teig

Brad Hutchings

Danny Thom

Jason Rupert Redgrave

Srinivasa Rao Malladi

Francois Ducaroir

Kwok K Chau

Jimmy Lee Reaves

Rong Pan

Krishnan Ramamurthy

Golf club stand

Some embodiments provide an integrated circuit ('IC') with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

Integrated circuit (IC) with primary and secondary networks and device containing such an IC

An integrated circuit (IC) that includes content addressable memories (CAM) is described. A CAM receives a key and searches through entries stored in the CAM for one or more entries that match the key. If a matching entry is found, the IC returns a storage address indicating a memory location at which the matching was found.

Content addressable memory in integrated circuit

A character programming method (10) whereby a synchronization character (17) can be determined in a determine encoding scheme operation (12) and a determine synchronization character operation (14). The synchronization character (17) can then be programmed into a synch character logic (26) of an integrated circuit (20) or a core (20) thereof. The synch character logic (26) can be programmed through a plurality of program pins (30) on the periphery of the integrated circuit (20) or by more sophisticated means such as by sending the programming from a sending integrated circuit (40) to a receiving integrated circuit (42) through a communications line (44).

Programmable synchronization character

Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be provided exclusively as firmware or software. A video decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, video header processing functions; and (b) hardware for implementing preparsing assist, macroblock reconstruction, and video display control functions. An audio decoder designed according to this procedure includes the following elements: (a) firmware or software for implementing, in conjunction with a CPU, decoding fields containing parameters for processing the audio data; and (b) hardware for implementing matrixing and windowing functions on the audio data.

Method for partitioning hardware and firmware tasks in digital

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Palo Alto, CA, United States of America

Marc A Miller