U.S. Philips Corporation

Koninklijke Philips Corporation N.V.

Nxp B.v.

Entropic Communications, Inc.

Marc A Duranton

Laurent Pasquier

Qin Zhao

Bernard Bru

Christian P Jousselin

Valérie Rivierre

Valerie Vier

Loic Geslin

Jean Gobert

Jacques-Ariel Sirat

The invention relates to a data processing system for performing a polyphase filtering. This circuit comprises functional units () able to perform polyphase filterings, and a memory device () for storing data and coefficients. The functional units receive in parallel data and coefficients coming from the memory device, calculate results from the data and coefficients and supply these results to the memory device.

Data processing circuit

The present invention relates to a communicating data system comprising devices () for routing said data that are interconnected by communication links, the data being transmitted in packets and a packet comprising a header. A transmitting part of a first routing device () comprises first storage means suitable for storing a value of at least one parameter from said header and for transmitting a coded value corresponding thereto, and first entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value after the latter is transmitted along a communication link (). A receiving part of a second routing device (), that is connected to the first routing device by the communication link, comprises second storage means suitable for storing the coded value coming from the communication link () and for transmitting the uncoded value corresponding thereto, and second entropy coding compression means which are suitable for recoding the uncoded value, the recoded value being stored instead of the coded value.

Data communication system according to a packet-switching principle

The invention relates to a processing system comprising a calculation device comprising at least one calculation unit (), a storage device and a system for switching between the storage device and the calculation device. In order to reduce the size of the switching system, the storage device comprises several banks of registers () for storing words, the switching system comprises at least one switching device () associated with each bank of registers and the calculation units exchange a word with a bank of registers by means of the associated switching device.

Data processing system

The present invention relates to a converter converting an input digital signal into an output digital signal. Said converter comprises in particular a set of shift registers able to contain samples of the input or output digital signal. It also comprises a calculation unit able to supply a shift signal () to said set of registers. Said calculation unit comprises a first storage unit () able to contain a value of a conversion ratio or of its inverse, so that the value stored is between 0 and 1. It also comprises a second storage unit () able to contain, at a cycle time i+1, i being an integer, a future signal () equal to a sum of a current signal () contained in the second unit at a cycle time i and of the content of the first storage unit. The shift signal then results from an exclusive OR function () between a most significant bit of the current signal () and a most significant bit of the future signal ().

Digital sampling frequency converter

A data processing device comprises a plurality of processors that are to access a memory system. The memory system comprises at least two memories The data processing device comprises a bus per memory. The buses are interconnected by at least one bridge. A processor is connected to a bus, and the data processing device comprises at least one memory table specifying with which memory an exchange of a data item between a processor and the memory system must be effected.

Device for processing data by means of a plurality of processors

A data processing arrangement () comprises a first processor (PROC) for providing successive sets of input data, a second processor (PROC) for receiving successive sets of output data and a memory system () comprising a plurality of memory circuits (MEM) for storing the input and output data. According to the invention, the data processing arrangement further comprises a master controller (MCP) for setting up memory system by means of control commands (CC) associated with a set of input data and a set of output data. These control commands are received in the memory system by a control unit (MCU). When a data (Di) from the set of input data is provided by the first processor, this control unit selects, on the basis of the control commands, a first memory circuit and generates a write-address (AD_W) in said first memory circuit. In the same way, when a data (Do) from the set of output data is required by the second processor, the control unit, on the basis of the control commands, selects a second memory circuit and generates a read-address (AD_R) in said second memory circuit. Thus, there is no need for the processors to provide addresses when they require or send data therefore leading to a simple data processing arrangement.

Data processing arrangement and memory system

A method of refreshing a dynamic memory intended for storing variables involved in operations performed by a processor, includes a step of planning in the course of which an order and a timing of the operations are established, a step of estimating a retention time specific to each variable, a step of forecasting at least one instant at which each variable must be refreshed, a step of placement in the course of which the variables are placed in the memory, a step of refreshing in the course of which the variables are refreshed at the instants defined during the forecasting step . The method allows a reduction in the latency times and in the consumption of current which are related to the refreshing. It is of particular benefit in systems where the real time constraint is important, for example, video data processing systems.

Method of refreshing a dynamic memory

A data-processing arrangement comprises a plurality of elementary circuits such as processing circuits &lsqb;PRC&rsqb; and memory circuits &lsqb;MEM&rsqb;. The data-processing arrangement further comprises a controller &lsqb;MCP&rsqb;. The controller &lsqb;MCP&rsqb; is programmed to successively apply, in response to a task-initialization data &lsqb;TID&rsqb;, control data &lsqb;CD&rsqb; to different subsets of elementary circuits. This causes the data-processing arrangement to process a block of data &lsqb;DB&rsqb; in accordance with a certain data-processing chain &lsqb;DPC&rsqb;. Each subset of elementary circuits implements a different element &lsqb;E&rsqb; of the data-processing chain &lsqb;DPC&rsqb;.

Data-processing arrangement comprising a plurality of processing and memory circuits

The invention relates to a method of communication between terminals and a central server, in which these terminals, whose principal function is MPEG-2 decoding, are diverted from this function, on request and after authorization, in order to partake in parallel in the common implementation of an auxiliary function under control of said server.

Method of communication between remote terminals and a central station

A data processor comprises an arithmetic logic unit &lsqb;ALU&rsqb; for carrying out an arithmetic or logic operation on a first and second input data &lsqb;OP , OP &rsqb;. It further comprises a stack &lsqb;STCK&rsqb; for storing data and for applying a data having a certain position &lsqb;P( )&rsqb; in the stack to the arithmetic logic unit &lsqb;ALU&rsqb; as the first input data &lsqb;OP &rsqb;. The data processor can execute an instruction &lsqb;INSTR&rsqb; which comprises an address &lsqb;ADDR&rsqb; indicating a memory location &lsqb;REG(i)&rsqb; among a plurality of memory locations &lsqb;REG&rsqb;. The address &lsqb;ADDR&rsqb; causes a data, which is contained in the memory location &lsqb;REG(i)&rsqb; that it indicates, to be applied to the arithmetic logic unit &lsqb;ALU&rsqb; as the second input data &lsqb;OP

Data processor comprising an arithmetic logic unit

A processor comprises an arithmetic logic unit (ALU) that co-operates with a stack arrangement (STCK). The processor is arranged to execute instructions (INSTR) which include a stack control field (SCF) and an opcode field (OPF) for controlling the stack arrangement (STCK) and the arithmetic logic unit (ALU), respectively.

Single instruction having op code and stack control field

Data-processing arrangement including an interrupt generator

A data-processing arrangement for a plurality of parallel data processors is disclosed. An operation carried out by at least one of the parallel processors is defined by an instruction word or code. The data-processing arrangement includes a control processor that makes compositions of instruction words using instruction-word composing software. A composition (VLIW) of instruction words defines operations which are to be carried out in parallel. The compositions are then provided to each parallel data processor as required. Storage of instruction-word composing software generally requires less memory space than storage of independent VLIW-s for each parallel data processor. The cost-saving this provides generally outweighs any additional costs associated with providing the control processor. Thus, the data-processing arrangement yields better cost and memory efficiency.

Parallel data processing

A method is described for addressing units (FU FU FU ) amongst a plurality of units having different addresses (ADD ADD ADD ) by use of an address word (AW), the addresses and the address word being composed of address elements. A tag word (TW) is transmitted to the plurality of units, the tag word defining which address elements of the address word are significant (S) and which address elements of the address word are non significant (X). The address word and the addresses of the units are compared and, a unit is addressed if the significant elements of the address word match the corresponding elements of the unit's address.

Method of addressing a plurality of addressable units by a single address word

A data processing arrangement comprises various data processors (P) and a memory arrangement (MA) for supplying input data (Di) to the data processors (P) and for storing output data (Do) from the data processors (P). The following steps are alternately carried out: a configuring step (CS) and a processing step (PS). In a configuration step (CS), the data processing arrangement is configured such that each data processor (P) will process a block (B) of data contained in the memory arrangement (MA) and then stop processing data. In a processing step (PS), the blocks (B) of data are processed in the respective data processors (P). A subsequent configuring step (CS) is carried out only when each data processor (P) has processed its block (B) of data (&forall;P: B&equals;PROC>CS). Such a data processing arrangement allows great versatility because different data processing chains can be realized without this requiring relatively complicated software.

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Boissy Saint Leger, France

Marc A Duranton