Sambanova Systems, Inc.

Maran Wilson

Arnav Goel

Conrad Alexander Turlik

Kin Hing Leung

Greg Dykema

Milad Sharif

Guoyao Feng

Kuan Zhou

Taylor Lee

Tianyu Sun

Manish K Shah

Paul Joseph Jordan

Ravinder Kumar

Qi Zheng

Ranen Chatterjee

Neal Sanghvi

Anand Misra

Pushkar Shridhar Nandkar

Joshua Earle Polzin

Shivam Raikundalia

Raghu Shenbagam

Anand Vayyala

A system for a data-parallel execution of at least two implementations of an application on reconfigurable processors with different layouts is presented. The system comprises a pool of reconfigurable data flow resources with data transfer resources that interconnect first and second reconfigurable processors having first and second layouts that impose respective first and second constraints for the data-parallel execution of the application. The system further comprises an archive of configuration files and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises first and second compilers that generate for the application, based on the respective first and second constraints, first and second configuration files that are stored in the archive of configuration files and adapted to be executed data-parallel compatible on respective first and second reconfigurable processors.

System of heterogeneous reconfigurable processors for the data-parallel execution of applications

A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.

System and method for user interactive pipelining of a computing application

A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.

Handling interrupts from a virtual function in a system with a reconfigurable processor

A system for executing an application on a pool of reconfigurable processors with first and second reconfigurable processors having first and second architectures that are different from each other is presented. The system comprises an archive of configuration files with first and second configuration files for executing the application on the first and second reconfigurable processors, respectively, and a host system that is operatively coupled to the first and second reconfigurable processors. The host system comprises a runtime processor that allocates reconfigurable processors for executing the application and an auto-discovery module that is configured to perform discovery of whether the reconfigurable processors include at least one of the first reconfigurable processors and whether the reconfigurable processors include at least one of the second reconfigurable processors. The runtime processor starts execution of the first and second configuration files in dependence upon the discovery of the auto-discovery module.

System for executing an application on heterogeneous reconfigurable processors

A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.

Hot-plug events in a pool of reconfigurable data flow resources

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Palo Alto, CA, United States of America

Maran Wilson