Boe Technology Group Co., Ltd.

Chengdu Boe Optoelectronics Technology Co., Ltd.

Maoying Liao

Huijuan Yang

Yi Zhang

Xiaoqing Shu

Tingliang Liu

Yang Zhou

Lingtong Li

Liheng Wei

Xin Zhang

Bo Zhang

Xiangdan Dong

Zhenhua Zhang

Linhong Han

Peng Xu

Jie Dai

Rong Wang

Junxiu Dai

Yixuan Long

Nanhao Chen

Tinghua Shang

Lu Bai

Hongwei Ma

Mengmeng Du

Bo Cheng

Ziyang Yu

Lianbin Liu

Tianci Chen

Biao Liu

Dan Cao

Guo Ning Liu

Shuangbin Yang

Yujing Li

Zhenggang Wu

Rendong Li

Provided is a dummy pixel circuit. The dummy pixel circuit is applicable to a display panel provided with two through vias and disposed between the two through vias, and includes a pixel sub-circuit and a dummy sub-circuit. The pixel sub-circuit includes one or more first transistors, wherein a control electrode of the first transistor is electrically connected to the first gate line. The dummy sub-circuit includes one or more second transistors, wherein a control electrode of the dummy sub-circuit is electrically connected to the first gate line, a first electrode of the second transistor is electrically connected to a first electrode of a corresponding one of the one or more first transistors, and a second electrode of the second transistor is electrically connected to a second electrode of the corresponding first transistor. One of the first transistors corresponds to at least one of the second transistors.

Dummy pixel circuit, display panel and display device

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y>Z.

Pixel circuit, method of driving pixel circuit, display panel, and display device

The disclosure provides a shift register including: input circuit configured to write signal from signal input terminal to third node in response to signal from first clock signal terminal; first control circuit configured to write voltage from first power terminal into first node in response to signals from preset control signal terminal and preset clock signal terminal; second control circuit configured to write voltage from second power terminal to first node in response to signal from signal input terminal; and output circuit configured to write voltage from second power terminal to signal output terminal in response to voltage at first node, and to write voltage from first power terminal to signal output terminal in response to voltage at fourth node. Third node is coupled to fourth node. The present disclosure further provides a gate driving circuit and a display apparatus.

Shift register, gate driving circuit and display apparatus

A shift register is configured to be applied to a display substrate including a plurality of rows of sub-pixels. The shift register is electrically connected to a single row of sub-pixels, and is further configured to transmit a scan signal and a reset signal to the single row of sub-pixels. The shift register includes a scan circuit and a reset circuit. The scan circuit is configured to output the scan signal due to cooperation of a first input signal, a first clock signal, a second clock signal, a first voltage signal and a second voltage signal. The reset circuit is configured to output the reset circuit due to cooperation of a second input signal, a third clock signal, a fourth clock signal, a third voltage signal and a fourth voltage signal. The scan circuit and the reset circuit are configured to output signals independently from each other.

Shift register having scan cicuit and reset circuit, scan driving circuit and display substrate

A display panel includes a pixel-driving circuit, wherein the display panel further includes: a base substrate, a second conductive layer and a third conductive layer. The second conductive layer is located on one side of the base substrate. The second conductive layer includes a first initial signal line, and the first initial signal line is configured to provide the first initial signal to the pixel-driving circuit. The third conductive layer is located on a side of the second conductive layer distal to the base substrate, the third conductive layer includes a second initial signal line, and the second initial signal line is configured to provide a second initial signal to the pixel-driving circuit, wherein sheet resistance of the first conductive layer is greater than that of the second conductive layer. The signal on the second initial signal line in the display panel has a smaller voltage drop.

Display panel and display device

A display panel and a display device are provided. The display panel includes a base substrate, a third conductive layer, a fourth conductive layer, a fifth conductive layer stacked in sequence. The third conductive layer includes first signal lines extending in a first direction and spaced apart in a second direction. The fourth conductive layer includes second signal lines extending in the first direction and spaced apart in the second direction. The second signal line includes second signal line segments spaced apart in the first direction. Each second signal line segment is electrically connected to a corresponding first signal line through a via hole. The fifth conductive layer includes electrode parts, the orthographic projections of at least some of the electrode parts on the base substrate are located in a gap between the orthographic projections of adjacent two second signal line segments in the same second signal line.

Disclosed are a display substrate and a display device. The display substrate includes a pixel circuit and a scan drive circuit, wherein the pixel circuit includes a write transistor and a scan signal line, the scan signal line is electrically connected with a control electrode of the write transistor, and the scan drive circuit includes a first scan clock signal line and a second scan clock signal line. A signal of the first scan clock signal line is a first clock signal, a signal of the second scan clock signal line is a second clock signal, and both of the first clock signal and the second clock signal are periodic clock signals. A duration of the first clock signal being a low-level signal in one period is different from a duration of the second clock signal being a low-level signal in one period.

Display substrate and display device

A method of driving a display device, where the display device includes a display substrate including a plurality of rows of pixel circuits, and in each pixel circuit, a reset compensation circuit and a data writing circuit are connected at a second node, and the reset compensation circuit is connected to a reset control signal line and a first voltage input terminal; in a driving stage, driving a light emitting device OLED connected to each of other rows of pixel circuits except a last row of pixel circuits further includes a charge maintenance stage performed after a light emission voltage generation stage; and in the stable display stage, all light emitting devices OLED simultaneously emit light; where in the charge maintenance stage, the first voltage input terminal is disconnected from the second node by the reset compensation circuit in response to control of a reset control signal.

Method of driving display device, including charge maintenance stage

A pixel driving circuit includes: a driving transistor connected to a first node, a second node and a third node; a first light-emitting control unit connected to the second node; a second light-emitting control unit connected to the third node and a fourth node; a first reset unit connected to the fourth node, and configured to load a second power supply voltage to the fourth node in response to a scan signal. One end of the light-emitting element is connected to the fourth node, and the other end of the light-emitting element is used for loading the second power supply voltage.

Pixel drive circuit, display panel and display device

An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by a first arm, and is spaced apart from a second adjacent data line by a second arm. An orthographic projection of a respective one of the plurality of voltage supply lines on the base substrate substantially covers at least 30% of an orthographic projection of the second arm on the base substrate.

Array substrate and display apparatus

A display substrate and a display device. In the display substrate, at least one of the inter-opening region, the first opening peripheral region and the second opening peripheral region includes a first virtual sub-pixel; the first signal line extends along a first direction and includes a first portion passing through the first opening peripheral region, the inter-opening region and the second opening peripheral region; the first portion passes through the first virtual sub-pixel, and the first virtual sub-pixel includes a first compensation capacitor, a first plate of the first compensation capacitor is in a same layer as the first portion of the first signal line and electrically connected with the first portion of the first signal line, and in a same layer as the second plate of the storage capacitor; the second plate is in a different layer from, insulated from, and overlaps with the first plate.

A display substrate and a display device. A first opening region includes a first opening and a first opening peripheral region surrounding the first opening; a display region surrounds the first opening region the first signal lines extend along the first direction; the second signal lines extend along a second direction; the second signal lines pass through the first opening peripheral region along the second direction, each second signal line includes a longitudinal winding portion in the first opening peripheral region; the longitudinal winding portion partially surrounds the first opening; the longitudinal winding portion closest to the first opening among longitudinal winding portion of the plurality of second signal lines is an edge longitudinal winding portion, and the first floating electrode is in a same layer as the edge longitudinal winding portion and is at a side of the edge longitudinal winding portion close to the first opening.

A display panel includes: a pixel driving circuit, a base substrate, a second conductive layer, a third conductive layer. The second conductive layer is disposed on a side of the base substrate, includes first signal lines, orthographic projections of the first signal lines extend in a first direction and spaced apart in a second direction, the first direction and the second direction intersect; the third conductive layer is disposed on a side of the second conductive layer away from the base substrate and includes second signal lines, orthographic projections of the second signal lines extend in the second direction and spaced apart in the first direction; the first signal lines and the second signal lines are configured to provide the same first signal to the pixel driving circuit, part of the first signal lines and the second signal lines are coupled through via holes.

Provided is a pixel circuit configured to drive, in an Xframe period, a light emitting device to emit light. The Xframe period includes Y data writing stages and Z light emitting stages, in which a ydata writing stage includes a first sub-stage to a third sub-stage. The pixel circuit includes: a driving transistor; a first reset module configured to transmit, in the first sub-stage, a first initialization signal to the driving transistor in response to a first scanning signal; a gating module configured to perform, in the second sub-stage, a threshold compensation on the driving transistor in response to a second scanning signal; and an input module configured to transmit, in the third sub-stage, a data signal to the driving transistor in response to a third scanning signal. X, Y, Z and y are positive integers, y≤Y, and Y≥Z.

An array substrate is provided. The array substrate includes a node connecting line in a same layer as a respective one of the plurality of voltage supply lines, connected to a first capacitor electrode through a first via, and connected to a semiconductor material layer through a second via; and an interference preventing block in a same layer as the second capacitor electrode. The respective one of the plurality of voltage supply lines is connected to the interference preventing block through a third via. The interference preventing block includes a first arm and a second arm. Along the first direction, a portion of the node connecting line at a position connecting to the semiconductor material layer through the second via is spaced apart from a first adjacent data line by the first arm, and is spaced apart from a second adjacent data line by the second arm.

Growing community of inventors

Beijing, China

Maoying Liao