Siliconware Precision Industries Co., Ltd.

Mao-Hua Yeh

Chieh-Lung Lai

Yi-Che Lai

Shih-Kuang Chiu

Lung-Yuan Wang

Chun-Hung Lu

Wen-Tsung Tseng

Feng Kao

Cheng-Yi Chen

Chih-Hsien Chiu

Chun-Chi Ke

Ying-Chou Tsai

Wen-Jung Tsai

Hung-Yuan Li

Hong-Da Chang

Yan-Heng Chen

Chang-Lun Lu

Hsien-Wen Chen

Bo-Siang Fang

Hung-Wen Liu

Shih-Liang Peng

Yi-Wei Liu

Hsinjou Lin

Shao-Meng Sim

Kuang-Sheng Wang

An electronic package and a method for fabricating the same are provided. Two packaging modules are stacked on each other. An area that an electronic package occupies a mother board is reduced during a subsequent process of fabricating an electronic product. Therefore, the electronic product has a reduced size.

Method for fabricating electronic package

Testing equipment is used in an antenna testing process, and includes a testing head having a perforation, and a testing device having a cylinder. The cylinder is disposed in the perforation to act as a cavity for the antenna testing process. Therefore, only the cylinder needs to be replaced when the antenna testing process is performed on different devices under test, with the whole testing head intact.

Test equipment and test device thereof

Electronic package and method for fabricating the same

The disclosure provides an electronic package and a method of manufacturing the same. The method is characterized by encapsulating an electronic component with a packaging layer and forming on an upper surface of the packaging layer a circuit structure that is electrically connected to the electronic component; and forming a stress-balancing layer on a portion of the lower surface of the packaging layer to balance the stress exerted on the upper and lower surfaces of the packaging layer, thereby reducing the overall package warpage and facilitating the manufacturing process.

Method for manufacturing electronic package

An electronic package and a method for fabricating the same are provided. An antenna frame, a first electronic component, and a second electronic component electrically connected to the antenna frame are disposed on a lower side of a carrying structure. An antenna structure is disposed on an upper side of the carrying structure and is electrically connected to the first electronic component. Therefore, two different types of antennas are integrated into an identical electronic package. Such the electronic package bonded to a circuit can transmit signals with two different wavelengths, even if the electronic package does not have any area increased.

Electronic package and method for manufacturing the same

A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

Semiconductor package and method of fabricating the same

A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one pillar disposed in the substrate body with the at least one pillar being free from penetrating the substrate body. When the semiconductor substrate is heated, the at least one pillar adjusts the expansion of upper and lower sides of the substrate body. Therefore, the upper and lower sides of the substrate body have substantially the same thermal deformation, and the substrate body is prevented from warpage.

Electronic package, semiconductor substrate of the electronic package, and method for manufacturing the electronic package

The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Package structure and fabrication method thereof

A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurance of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.

A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Growing community of inventors

Taichung, Taiwan

Mao-Hua Yeh