Taiwan Semiconductor Manufacturing Comp. Ltd.

Mao-Hsuan Chou

Chih-Hsien Chang

Ruey-Bin Sheen

Ya-Tin Chang

Tsung-Hsien Tsai

Min-Shueh Yuan

Chien-Hung Zordius Chen

Chih-Chiang Chang

Chung-Chieh Yang

Jinn-Yeh Chien

Chih-hsien Chang

Matt Li

The present disclosure provides a system of measuring capacitance of a device-under-test (DUT). The system includes first switch, second switch, and a capacitance measurement device. The first switch is configured to receive a supply voltage. The first and second switches are electrically connected to the DUT. The capacitance measurement device is configured to provide a first pair of non-overlapping periodic signals with a first frequency, and a second pair of non-overlapping periodic signals with a second frequency. The second frequency is β times the first frequency. When the first switch and the second switch receive the first pair of non-overlapping periodic signals, a first current is transmitted through the first switch and the second switch. When the first switch and the second switch receive the second pair of non-overlapping periodic signals, a second current is transmitted through the first switch and the second switch.

System and method of measuring capacitance of device-under-test

A device includes a phase detector circuit, a charge pump circuit, a sample and hold circuit, a comparator, and a controller. The phase detector circuit detects a clock skew between a reference signal and an input signal. The charge pump circuit translates the clock skew into a voltage. A sample and hold circuit samples the voltage, at a first time, and maintain the sampled voltage until a second time. The comparator (i) detects a loop gain associated with the input signal based on the sampled voltage and the voltage at the second time and (ii) outputs a loop gain signal for adjustment of the input signal. The controller is coupled to the phase detector, the comparator, and the sample and hold circuit. The controller generates a plurality of control signals for automatically controlling operation of the phase detector, the comparator, and the sample and hold circuit.

Loop gain auto calibration using loop gain detector

A counter signal counting at a frequency of a clock signal is generated. Among a plurality of different numeric ranges corresponding to a plurality of different thresholds, a threshold corresponding to a numeric range containing a frequency ratio is selected. In response to the counter signal reaching the selected threshold, a logic level of an output signal is switched.

Compensation circuit and method for frequency divider circuit

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period; a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

Method and apparatus for precision phase skew generation

A system, a method and a built-in phase noise measurement apparatus are introduced. The built-in phase noise measurement apparatus includes a first DLL and a TDC, in which the first DLL circuit controls a delay of a first signal to generate a second signal based on a control code, tune the control code until a phase of the second signal is aligned to a phase of a reference clock signal, and record a value of the control code when the phase of the second signal is aligned to the phase of the reference clock signal. The DLL circuit controls the delay of the first signal based on the value of the control code after the phase of the second signal is aligned to the phase of the reference clock signal. The TDC determines the phase noise of the first signal based on the reference clock signal and the second signal.

Apparatus, system and method for phase noise measurement

An apparatus and method for providing a phase noise built-in self test (BIST) circuit are disclosed herein. In some embodiments, a method and apparatus for forming a multi-stage noise shaping (MASH) type high-order delta sigma (&#x394;&#x3a3;) time-to-digital converter (TDC) are disclosed. In some embodiments, an apparatus includes a plurality of first-order &#x394;&#x3a3; TDCs formed in an integrated circuit (IC) chip, wherein each of the first-order &#x394;&#x3a3; TDCs are connected to one another in a MASH type configuration to provide the MASH type high-order &#x394;&#x3a3; TDC, wherein the MASH type high-order &#x394;&#x3a3; TDC is configured to measure the phase noise of a device under text (DUT).

Built-in self test circuit for measuring phase noise of a phase locked loop

A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle lower than 50% and greater than 1/r, where r is the frequency ratio.

Frequency divider circuit, and method for frequency divider circuit

A method and apparatus of generating precision phase skews is disclosed. In some embodiments, a phase skew generator includes: a charge pump having a first mode of operation and a second mode of operation, wherein the first mode of operation provides a first current path during a first time period, and the second mode of operation provides a second current path during a second time period following the first time period, a sample and hold circuit, coupled to a capacitor, and configured to sample a voltage level of the capacitor at predetermined times and provide an output voltage during a third time period following the second time period; and a voltage controlled delay line, coupled to the sample and hold circuit, and having M delay line stages each configured to output a signal having a phase skew offset with respect to preceding or succeeding signal.

A delay-locked loop includes a phase detector configured to detect a phase difference between a first clock and a second clock, a charge pump configured to increase a charge amount at a capacitive load in accordance with a first charge amount and decrease the charge amount at the capacitive load in accordance with a second charge amount based on a phase difference provided by the phase detector, a sample and hold circuit configured to receive the charge amount from the capacitive load and hold the charge amount, and a voltage control delay line configured to select a delay amount based on the charge amount received from the sample and hold circuit. At least one parameter of the delay-locked loop is configured such that a desired pump current ratio of a delay cell is achieved by adjusting a delay amount of the delay cell and/or an amount of current coupled to the delay cell.

Voltage controlled delay line gain calibration

A frequency divider circuit includes a counter configured to generate a counter signal responsive to a frequency of a clock signal and a frequency ratio, and a compensation circuit coupled to the counter, and configured to generate an output signal. The output signal has a frequency equal to the frequency of the clock signal divided by a frequency ratio, and a duty cycle greater than 1/r, where r is the frequency ratio.

Growing community of inventors

Hsinchu County, Taiwan

Mao-Hsuan Chou