Lancaster University Business Enterprises Limited

University of Lancaster

Manus Hayne

Peter David Hodgson

Dominic Lane

A memory cell comprises a floating gate being disposed between a control gate and a channel, the floating gate being electrically isolated from the control gate and the channel by charge barriers and being configured to enable the selective passage of charge carriers into and out of the floating gate to provide occupancy states of the floating gate. The channel is arranged to provide a minimum threshold voltage to be applied between a control gate and the substrate for introducing charge carriers into the channel from the substrate to make the channel conductive, the minimum threshold voltage being dependent on the occupancy state of the floating gate, such that a read voltage may be applied between the control gate and the substrate that will provide a conductive channel for a first occupancy state of the floating gate and a non-conductive channel for a second occupancy state of the floating gate.

Electronic memory devices

A vertical-cavity surface-emitting laser ('VCSEL') has at least a substrate, electrical contacts, a first mirror region, a second mirror region and an active region between the mirror regions; where the mirror regions comprise distributed Bragg reflectors formed of a plurality of layers; laser emission is from at least one gallium arsenide antimonide nanostructure in the active region; and each said nanostructure contains more antimony atoms than arsenic atoms.

Vertical-cavity surface-emitting laser

A memory cell for storing one or more bits of information has a control gate, a source terminal and a drain terminal. A semiconductor substrate is located between the source and drain terminals, and a floating gate is disposed between the control gate and the semiconductor substrate. The floating gate is electrically isolated from the control gate by a charge trapping barrier, and is electrically isolated from the semiconductor substrate by a charge blocking barrier. At least one of the charge trapping barrier and the charge blocking barrier contains a III-V semiconductor material. The charge trapping barrier is adapted to enable the selective passage of charge carriers between the control gate and the floating gate, in use, to modify the one or more bits of information stored by the memory cell.

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Lancashire, United Kingdom

Manus Hayne