Spansion Llc.

Cypress Semiconductor Corporation

Other

Advanced Micro Devices Corporation

Manuj Rathor

Steven C Avanzino

Suzette Keefe Pangrle

Sameer S Haddad

Krishnaswamy Ramkumar

An Chen

Fei Wang

Matthew S Buynoski

Bryan K Choo

Zhida Lan

James J Xie

Michael Vanbuskirk

Christie Marrian

Kevin Song

Jeffrey Allan Shields

Nicholas H Tripsas

Loren T Lancaster

Joffre F Bernard

Andy C Wei

Alain Paul Blosse

Anthony Mowry

James E Nulty

Andreas Gehring

Jianmin Qiao

Sanjay M Thekdi

Mehran G Sedigh

Biju Parameshwaran

Fred B Jenne

Jeffery A Shields

Dutta Saurabh Chowdhury

James Xie

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

Damascene metal-insulator-metal (MIM) device with improved scaleability

In an electronic device, a diode and a resistive memory device are connected in series. The diode may take a variety of forms, including oxide or silicon layers, and one of the layers of the diode may make up a layer of the resistive memory device which is in series with that diode.

Diode and resistive memory device structures

The present memory device includes first and second electrodes, first and second insulating layers between the electrodes, the first insulating layer being in contact with the first electrode, the second insulating layer being in contact with the second electrode, and a metal layer between the first and second insulating layers. Further included may be a first oxide layer between and in contact with the first insulating layer and the metal layer, and a second oxide layer between and in contact with the second insulating layer and the metal layer.

Metal-insulator-metal-insulator-metal (MIMIM) memory device

The present resistive memory device includes first and second electrodes. An active layer is situated between the first and second electrodes. The active layer with advantage has a thermal conductivity of 0.02 W/Kcm or less, and is surrounded by a body in contact with the layer, the body having a thermal conductivity of 0.01 W/Kcm or less.

Memory device with improved performance

An electronic device includes a first electrode, a second electrode and an insulating layer between the first and second electrodes, which insulating layer may be susceptible to reduction by H. A gettering layer is provided on and in contact with the first electrode, the gettering layer acting as a protective layer for substantially avoiding reduction of the insulating layer by capturing and immobilizing H. A glue layer may be provided between the gettering layer and first electrode. An additional gettering layer may be provided on and in contact with the second electrode, and a glue layer may be provided between the second electrode and additional gettering layer.

Gettering/stop layer for prevention of reduction of insulating oxide in metal-insulator-metal device

The present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening in the dielectric layer, providing a switching body in the opening, and providing a second conductive body in the opening.

Damascene metal-insulator-metal (MIM) device

In the present electronic test structure comprising, a conductor is provided, overlying a substrate. An electronic device overlies a portion of the conductor and includes a first electrode connected to the conductor, a second electrode, and an insulating layer between the first and second electrodes. A portion of the conductor is exposed for access thereto.

Test structures for development of metal-insulator-metal (MIM) devices

A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. The first transistor element comprises at least one first amorphous region and the second transistor element comprises at least one second amorphous region. A stress-creating layer is formed over the first transistor element. The stress-creating layer does not cover the second transistor element. A first annealing process is performed. The first annealing process is adapted to re-crystallize the first amorphous region and the second amorphous region. After the first annealing process, a second annealing process is performed. The stress-creating layer remains on the semiconductor substrate during the second annealing process.

Method of forming a semiconductor structure comprising a field effect transistor having a stressed channel region

In one embodiment, a method of fabricating an integrated circuit includes the steps of: (i) forming composite spacers on sidewalls of a transistor gate, each of the composite spacers comprising a first liner having a stepped portion and a disposable spacer material over the stepped portion; (ii) forming a source/drain region by performing ion implantation through a portion of the first liner over the source/drain region; (iii) replacing the disposable spacer material with a second liner formed over the first liner after forming the source/drain region; (iv) forming a pre-metal dielectric over the second liner; and (v) forming a self-aligned contact through the pre-metal dielectric. Among other advantages, the method allows for an increased contact area for a self-aligned contact.

Increasing self-aligned contact areas in integrated circuits using a disposable spacer

A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step), forming a charge storing dielectric (step), and forming a top insulating layer (step) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Method of manufacturing an oxide-nitride-oxide (ONO) dielectric for SONOS-type devices

A method of forming a charge storing layer is disclosed. According to an embodiment, a method may include the steps of forming a first portion of a charge storing layer with a first gas flow rate ratio (step ), forming at least a second portion of the charge storing layer by changing to a second gas flow rate ratio that is different than the first gas flow rate ratio (step ), and forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio that is different than the second gas flow rate ratio (step ).

Method of manufacturing a dielectric layer for a silicon-oxide-nitride-oxide-silicon (SONOS) type devices

Growing community of inventors

Milpitas, CA, United States of America

Manuj Rathor