Micron Technology Incorporated

Manuela Scognamiglio

Federico Tiziani

Danilo Caraccio

Giovanni Campardo

Massimo Iaculo

Antonino Pollio

Claudio Giaccio

Ornella Vitale

Andrea Ghilardelli

Gian Pietro Vanalli

Stefano Corno

Massimiliano Magni

Emanuele Confalonieri

Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with multiple memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the multiple memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

Controller to manage NAND memories

Various embodiments disclose a controller to manage memory devices. In an exemplary method, signals are exchanged with a host processor to allow the host processor to communicate with a plurality of memory devices in a memory stack as a single device, regardless of an actual number of memory devices within the memory stack. Power is provided to a single one of the plurality of the memory devices in the memory stack at a time to reduce power consumption. Other methods, apparatuses, and devices are also disclosed.

In various embodiments, a single virtualized error correcting code (ECC) NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack. In various embodiments, a controller manages a plurality of NAND memory devices. The controller provides power to a select one of the plurality of NAND memory devices at a time to conserve overall power consumption of the storage system.

A system and method are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores error correction information related to the blocks storing the data. The first memory and the second memory are of different types.

Secondary memory to store error correction information

A method and system are disclosed in which a first non-volatile memory includes blocks that store data, and a second memory that stores overhead information related to the blocks storing the data. The amount of the second memory storing the overhead information related to the at least one block of the plurality of blocks is varied.

Secondary memory to store a varying amount of overhead information

A single virtualized ECC NAND controller executes an ECC algorithm and manages a stack of NAND flash memories. The virtualized ECC NAND controller allows the host processor to drive the stack of flash memory devices as a single NAND chip while the controller redirects the data to the selected NAND memory device in the stack.

Controller to execute error correcting code algorithms and manage NAND memories

Various embodiments comprise apparatuses and methods including a memory controller to control a non-volatile memory array. The memory controller includes a memory array interface coupled to the non-volatile memory array to perform reads and writes on the non-volatile memory array. An overwrite module is configured to write a desired bit value to a specific memory cell within the non-volatile memory array, after receiving the desired bit value and a logical address, regardless of an original value of the memory cell Additional apparatuses and methods are described.

Control and operation of non-volatile memory

Embodiments for providing improved reliability or extended life for a non-volatile memory component may comprise a secondary non-volatile memory component to store error correction information, for example.

Secondary memory element for non-volatile memory

A memory controller for a phase change memory (PCM) that can be used on a storage bus interface is described. In one example, the memory controller includes an external bus interface coupled to an external bus to communicate read and write instructions with an external device, a memory array interface coupled to a memory array to perform reads and writes on a memory array, and an overwrite module to write a desired value to a desired address of the memory array.

Growing community of inventors

Burago Molgora, Italy

Manuela Scognamiglio