International Business Machines Corporation

Robert Boschgmbh

Manuela Niekisch

Silvia Melitta Mueller

Kerstin Claudia Schelm

Michael Klaus Kroener

Adrian Haug

Dieter Bruss

Martin Karle

Thomas Tietjen

Philipp Brechel

Wei Ling

Silke Bruening

Steven R Carlough

Michael Klein

Klaus Michael Kroener

Ibrahim Duran

Stefan Kummler

Christoph Senneka

Daniel Wettach

A method for operating a computing arrangement. The computing arrangement includes: a plurality of single-chip systems, wherein the single-chip systems are configured to obtain the same sensor data, and at least one degradation mechanism configured to perform functions of a failed single-chip system on another single-chip system. In the method, when a failure of at least one of the single-chip systems is sensed, a switch takes place to another single-chip system to perform a function assigned to the failed single-chip system. A degradation mechanism is additionally performed.

Method for operating a control unit

A method for monitoring operation of at least one electrical load for a vehicle. A comparison of an actual value of an operating parameter with four threshold values is performed. A monitoring signal is also generated dependent on a result of the comparison, the monitoring signal being generated with a first signal characteristic if the actual value lies between the first threshold value and the third threshold value or between the second threshold value and the fourth threshold value, or being generated with a second signal characteristic if the actual value lies above the third threshold value or below the fourth threshold value. The first signal characteristic effects activation of at least one safety function that maintains an active operating state of the at least one electrical load. The second signal characteristic effects deactivation of the at least one electrical load.

Method and device for monitoring operation of at least one electrical load for a vehicle

Performing an arithmetic operation in a data processing unit, including calculating a number of iterations for performing the arithmetic operation with a given number of bits per iteration. The number of bits per iteration is a positive natural number. A number of consecutive digit positions of a digit in a sequence of bits represented in the data processing unit is counted. The length of the sequence is a multiple of the number of bits per iteration. A quotient of the number of consecutive digit positions divided by the number of bits per iteration is calculated, as well as a remainder of the division.

Calculation of a number of iterations

An initializable repair circuit and method are provided to facilitate, when enabled, selective replacement of a table-driven output value provided by a lookup structure. The initializable repair circuit includes a compare circuit to identify a cell of the lookup structure based, at least in part, on a first input value and a second input value. The table-driven output value is ascertained, at least in part, using a cell value of the identified cell. The initializable repair circuit further includes a repair enable register and a logic circuit. The repair enable register contains an enable repair indicator to be set when at least one cell value is known to be incorrect, and the logic circuit replaces the incorrect table-driven output value provided by the lookup structure with an initialized replacement value based, at least in part, on the enable repair indicator being set in the repair enable register.

Initializable repair circuit for selectively replacing a table-driven output

A logic circuit and a method using thereof for zero detection of a sum of inputs without performing an addition. The logic circuit and the method using thereof perform a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof include bitwise XOR, XNOR, and OR operations, an OR-reduction, an AND reduction, and a control signal that switches between a true mathematical zero check and a zero check for trailing N-bits. The logic circuit and the method using thereof have less timing delay than an adder or a leading zero anticipator for a zero check. The logic circuit and the method using thereof use less logic gates and therefore less area and less power are needed. The logic circuit and the method using thereof have a great advantage for the zero check of large input vectors.

Zero detection of a sum of inputs without performing an addition

Methods, systems and computer program products for computing and summing up multiple products in a single multiplier are provided. Aspects include receiving a first number and a second number, creating partial products of the first number and the second number based on a multiplication of the first number and the second number, and reducing the number of partial products to create an intermediate result. Aspects also include receiving a third number and a fourth number, creating partial products of the third number and the fourth number based on a multiplication of the third number and the fourth number, creating a reduction tree and adding the intermediate result to the reduction tree. Aspects further include reducing the number of partial products in the reduction tree to create a second sum value and a second carry value and adding the second sum value and the second carry value to create a result.

Computing and summing up multiple products in a single multiplier

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Gechingen, Germany

Manuela Niekisch