Infineon Technologies Ag

Manuela Meier

Andreas Graefe

Viola Rieger

Longli Yu

Albrecht Mayer

Joerg Syassen

Avni Bildhaiya

In some implementations, a device may identify a set of characteristics of a frame. The device may compute a first key index associated with the frame based on the set of characteristics and using a first key index function. The device may determine whether the first key index is associated with any collision entries from a set of collision entries. The device may determine a set of security parameters associated with the frame using a particular key index. The particular key index is either the first key index when the first key index is not associated with any collision entries from the set of collision entries, or is a second key index when the first key index is associated with a collision entry from the set of collision entries.

Secure communication acceleration using a frame classifier

A device includes a safety domain having a processing unit and a memory and is configured to provide at least one functionality and to implement one more safety measures for detecting faults. The safety domain is configured to transmit at least one alarm signal indicating one or more detected errors in response to detecting the faults. The device further includes a security domain having a processing unit and a memory and is configured to provide cryptographic services and to obtain alarm signals. The security domain is configured to perform security-related operations in a secure state in response to obtaining an alarm signal from the safety domain.

Security device and methods of operating a security device

A device may include a buffer memory to buffer frames received or to be transmitted via a plurality of ports of the device. The device may include at least one frame processor to process frames. The device may include a buffer manager to store a frame in the buffer memory. The buffer manager may allocate at least one buffer control block (BCB) to the frame based on storing the frame in the buffer memory. The buffer manager may allocate a frame control block (FCB) to the frame. The FCB may include information that identifies the at least one BCB. The buffer manager may perform one or more queueing operations in association with processing of the frame by the at least one frame processor. The one or more queuing operations may be performed using information associated with the FCB.

Buffer management in an ethernet switch

A system may include a cryptographic accelerator to generate a first check value based on a payload received in a message, and provide the first check value to a first comparator and to a second comparator. The system may include the first comparator to receive the first check value from the cryptographic accelerator, determine whether the first check value matches a second check value, the second check value being a check value received in the message, and provide a first output indicating whether the first check value matches the second check value. The system may include the second comparator to receive the first check value from the cryptographic accelerator, determine whether the first check value matches the second check value, and provide a second output indicating whether the first check value matches the second check value.

System for an improved safety and security check

A system may include a first processing component arranged in a secure domain of the system. The system may include a second processing component arranged outside of the secure domain of the system. The system may include one or more hardware accelerators to perform operations in association with providing communication security for the system. The one or more hardware accelerators may be accessible by the first processing component via a channel in the secure domain. The one or more hardware accelerators may be accessible by at least the second processing component via a channel outside of the secure domain.

Secure software interface

A cryptographic accelerator may include an input buffer to store an additional authenticated data (AAD) portion of a message and a plain text portion of the message. The cryptographic accelerator may include a cryptographic engine to generate cipher text using the plain text portion of the message, generate a message authentication code (MAC) using the AAD portion and either the plain text portion or the cipher text, determine a configuration for creating an assembled message in an output buffer of the cryptographic accelerator, and provide at least the cipher text to the output buffer to create the assembled message in the output buffer according to the configuration. The cryptographic accelerator may include the output buffer to provide the assembled message.

Automatic message assembly during a cryptographic operation

A cryptographic accelerator may include an input buffer to store first data, including a first portion of a message, in a first address range and second data, including a second portion of the message, in a second address range. The cryptographic accelerator may include one or more components to determine lengths of the first and second portions, read the first portion from the first address range, discard any dummy data in the first address range based on an indication of an endpoint of the first data in the first address range, read the second portion from the second address range, and discard any dummy data in the second address range based on an indication of an endpoint of the second data in the second address range. The cryptographic accelerator may include a cryptographic engine to perform a cryptographic operation using the first portion and the second portion.

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Munich, Germany

Manuela Meier