International Business Machines Corporation

Eidgenossische Technische Hochschule Zurich

Oxford University Innovation Ltd

Eth Zurich

University of Münster

University of Exeter

Manuel Le Gallo-Bourdeau

Abu Sebastian

Evangelos Stavros Eleftheriou

Giovanni Cherubini

Abbas Rahimi

Kumudu Geethan Karunaratne

Riduan Khaddam-Aljameh

Irem Boybat Kara

Christophe Piveteau

Luca Benini

Lukas Kull

Ghazi Sarwat Syed

Vara Sudananda Prasad Jonnalagadda

Benedikt J Kersting

Konstantinos Bekas

Tomas Tuma

Alessandro Curioni

Milos Stanisavljevic

Nandakumar Sasidharan Rajalekshmi

Vinay Manikrao Joshi

Angeliki Pantazi

Pier Andrea Francese

Adelmo Cristiano Innocenza Malossi

Athanasios Vasilopoulos

Julian Röttger Büchel

Nikolas Ioannou

Thomas Helmut Toifl

Timothy Mathew Philip

Harish Bhaskaran

Wolfram Pernice

Iason Giannopoulos

Christopher David Wright

Nathan Youngblood

Xuan Li

Benedikt Kersting

Igor Krawczuk

Johannes Feldmann

Simon Haefeli

Frédéric Elias Odermatt

Julian Buechel

Provided is a method, device, and computer program product for programming a set of first elements onto a computational memory. The computational memory allows for performing a computation task from a set of second elements that encode the set of first elements in the computational memory, respectively. The method includes performing the computation task by the computational memory using the set of second elements and adapting at least part of the set of second elements in the computational memory based on a measured result of the computation task, until the measured result of the computation task fulfils an accuracy condition.

Programming elements onto a computational memory

The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.

Compensating non-ideality of a neuromorphic memory device

The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.

Accurate programming of analog memory devices of in-memory processing devices having a crossbar array structure

The present disclosure relates to a method for classifying a query information element using the similarity between the query information element and a set of support information elements. A resulting set of similarity scores is transformed using a sharpening function such that the transformed scores are decreasing as negative similarity scores increase and the transformed scores are increasing as positive similarity scores increase. A class of the query information element is determined based on the transformed similarity scores.

Memory-augmented neural network system

A device for performing a matrix-vector multiplication of a matrix with a vector. The device comprising a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The memory crossbar array further comprises one or more write-assist wires and one or more corresponding arrays of switching elements. The write-assist wires are connectable via the switching elements to the plurality of column lines.

Resistive memory device for matrix-vector multiplications

The exemplary embodiments disclose a method, a computer program product, and a computer system for a gated recurrent neural network (RNN). The exemplary embodiments may include providing an element processor, providing a distinct memory array for a respective set of one or more elements of a hidden state vector, storing in the memory array a group of columns of weight matrices that enable a computation of the set of one or more elements, computing one or more elements of each of multiple activation vectors using a set of one or more columns of the group of columns associated with each of the multiple activation vectors, and performing by the element processor an elementwise gating operation on computed elements, resulting in the set of one or more elements.

Gated unit for a gated recurrent neural network

The present disclosure relates to a method for representing an ordered group of symbols with a hypervector. The method comprises sequentially applying on at least part of the input hypervector associated with a current symbol a predefined number of circular shift operations associated with the current symbol, resulting in a shifted hypervector. A rotate operation may be applied on the shifted hypervector, resulting in an output hypervector. If the current symbol is not the last symbol of the ordered group of symbols the output hypervector may be provided as the input hypervector associated with a subsequent symbol of the current symbol; otherwise, the output hypervector of the last symbol of the ordered group of symbols may be provided as a hypervector that represents the ordered group of symbols.

Representation of an ordered group of symbols by hypervectors

The invention is notably directed to a device for performing a matrix-vector multiplication of a matrix with a vector. The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element. The device further comprises a readout circuit configured to perform read operations by applying positive read voltages of one or more first amplitudes and negative read voltages of one or more second amplitudes corresponding to the one or more first amplitudes. The one or more first amplitudes and the corresponding one or more second amplitudes are different from each other, thereby correcting polarity dependent current asymmetricities.

Device for matrix-vector multiplications

A method of operating a neuromorphic system is provided. The method includes applying voltage signals across input lines of a crossbar array structure, the crossbar array structure including rows and columns interconnected at junctions via programmable electronic devices, the rows including the input lines for applying voltage signals across the electronic devices and the columns including output lines for outputting currents. The method also includes correcting, via a correction unit connected to the output lines, each of the output currents obtained at the output lines according to an affine transformation to compensate for temporal conductance variations in the electronic devices.

Conductance drift corrections in neuromorphic systems based on crossbar array structures

A projected memory device includes a carbon-based projection component. The device includes two electrodes, a memory segment, and a projection component. The projection component and the memory segment form a dual element that connects the two electrodes. The projection component extends parallel to and in contact with the memory segment. The memory segment includes a resistive memory material, while the projection component includes a thin film of non-insulating material that essentially comprises carbon. In a particular implementation, the non-insulating material and the projection component essentially comprises amorphous carbon. Using carbon and, in particular, amorphous carbon, as a main component of the projection component, allows unprecedented flexibility to be achieved when tuning the electrical resistance of the projection component.

Projected memory device with carbon-based projection component

A memory device enabling a reduced minimal conductance state may be provided. The device comprises a first electrode, a second electrode and phase-change material between the first electrode and the second electrode, wherein the phase-change material enables a plurality of conductivity states depending on the ratio between a crystalline and an amorphous phase of the phase-change material. The memory device comprises additionally a projection layer portion in a region between the first electrode and the second electrode. Thereby, an area directly covered by the phase-change material in the amorphous phase in a reset state of the memory device is larger than an area of the projection layer portion oriented to the phase-change material, such that a discontinuity in the conductance states of the memory device is created and a reduced minimal conductance state of the memory device in a reset state is enabled.

Projected memory device with reduced minimum conductance state

A system for hyper-dimensional computing for inference tasks may be provided. The device comprises an item memory for storing hyper-dimensional item vectors, a query transformation unit connected to the item memory, the query transformation unit being adapted for forming a hyper-dimensional query vector from a query input and hyper-dimensional base vectors stored in the item memory, and an associative memory adapted for storing a plurality of hyper-dimensional profile vectors and for determining a distance between the hyper-dimensional query vector and the plurality of hyper-dimensional profile vectors, wherein the item memory and the associative memory are adapted for in-memory computing using memristive devices.

Device for hyper-dimensional computing tasks

A co-processor for performing a matrix multiplication of an input matrix with a data matrix in one step may be provided. The co-processor receives input signals for the input matrix as optical signals. A plurality of photonic memory elements is arranged at crossing points of an optical waveguide crossbar array. The plurality of memory elements is configured to store values of the data matrix. Input signals are connected to input lines of the optical waveguide crossbar array. Output lines of the optical waveguide crossbar array represent a dot-product between a respective column of the optical waveguide crossbar array and the received input signals, and values of elements of the input matrix to be multiplied with the data matrix correspond to light intensities received at input lines of the respective photonic memory elements. Additionally, different wavelengths are used for each column of the input matrix optical signals.

Photonic in-memory co-processor for convolutional operations

Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n&#x2265;1 and (p+n+m)=N where m&#x2265;0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Training of artificial neural networks

The present disclosure relates to an electronic system for computing items of an outer product matrix, for each item of at least part of the items of the matrix. The system is configured to receive a pair of real numbers of two vectors, the pair corresponding to the item. The system is further configured to compute a stochastic representation of the real numbers resulting in two sets of bits, the set of bits comprising a subset of bits representing the real number and a sign bit indicative of the sign of the real number. The system is further configured to perform a sequence of digital operations using the two sets of bits to provide a representation of the item.

Electronic system for computing items of an outer product matrix

Growing community of inventors

Zurich, Switzerland

Manuel Le Gallo-Bourdeau