The Boeing Company

Manuel F Cabanas-Holmen

Ethan Harrison Cannon

Salim A Rabaa

Alfio Zanchi

Mark Joseph Clemen, Jr

Jeffrey Maharrey

Mark Yao

Roger Brees

Jeff Maharrey

A solid-state device having a substrate that receives an ionizing radiation, logic circuits, integrity circuits, and a collection circuit. The logic circuits are operational to perform logic functions. The logic circuits are located in an area on the substrate, and are individually susceptible to a possible corruption by the ionizing radiation. Each integrity cell is initialized to a predetermined state. The integrity cells are located in the area on the substrate, arranged in a pattern neighboring the logic circuits, and individually susceptible to disrupting the predetermined state in response to the ionizing radiation. The collection circuit is located on the substrate. The collection circuit is operational to read the plurality of integrity cells, and assert a report signal that identifies the possible corruption in a subset of the logic circuits due to the ionizing radiation in response to reading an incorrect state in a neighboring one of the integrity cells.

Radiation induced error detection in solid-state devices

A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.

Radiation hardened flip-flop circuit for mitigating single event transients

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

Direct measurement test structures for measuring static random access memory static noise margin

Systems, methods, and apparatus for complementary self-limiting logic are disclosed. In one or more embodiments, a method for mitigating errors caused by transients in a logic gate transistor comprises biasing, by a first stage of transistors, a second stage of transistors such that a voltage potential across terminals of each of the transistors of the second stage are at an equal voltage potential. The method further comprises biasing, by the second stage of transistors, the logic gate transistor such that a voltage potential across terminals of the logic gate transistor are at an equal voltage potential, thereby ensuring that the transients will not cause the logic gate transistor to erroneously change logic states when the logic gate transistor is in a logically off state.

Complementary self-limiting logic

A self-optimizing circuit for a FD-SOI device includes a static biasing circuit, a dosimeter, a reference circuit, an amplifier, a voltage source, and a feedback circuit. The static biasing circuit supplies a first bias. The dosimeter includes a dosimeter FD-SOI device and generates a dosimeter voltage sensitive to parametric shifts in the primary FD-SOI device. The reference circuit supplies a reference voltage. The amplifier is coupled to the dosimeter and the reference circuit, and supplies a second bias at an output of the static biasing circuit, the second bias proportional to a difference between the dosimeter voltage and the reference voltage. The voltage source generates a drive voltage to which the first bias and the second bias are referenced. The feedback circuit regulates supply of the drive voltage to a well of the dosimeter FD-SOI device according to the first bias and the second bias.

Self-optimizing circuits for mitigating total ionizing dose effects, temperature drifts, and aging phenomena in fully-depleted silicon-on-insulator technologies

A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.

Filtered radiation hardened flip flop with reduced power consumption

An interleaved filter circuit has a delay element configured to receive an input signal. An interleaved output buffer has a first input which receives the input signal and a second input which receives the output of the delay element. An output of the interleaved output buffer is driven when the first input and the second input are at a same logic level.

Interleaved transient filter

The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Growing community of inventors

Roy, WA, United States of America

Manuel F Cabanas-Holmen