International Business Machines Corporation

Manu J Tejwani

Rajiv V Joshi

Seshadri Subbanna

Kris V Srikrishnan

Subramanian Srikanteswara Iyer

Jonathan Daniel Chapple-Sokol

Joseph F Shepard

Scott R Stiffler

Bruce A Ek

Edward J Vishnesky

Toshio Mii

Adrian Roger Powell

Philip Michael Pitner

Louis L Hsu

Dominic Joseph Schepis

Jack Oon Chu

Andrew Herbert Simon

Louis Lu-Chen Hsu

Richard Anthony Conti

David Edward Kotecki

John M Aitken

Paul Andrew Ronsheim

Ronald W Knepper

Russell C Lange

Robert K Cook

Bob H Yun

Vijay P Kesan

Subodh K Kulkarni

Jack C Chu

A soft metal conductor for use in a semiconductor device that has an upper-most layer consisting of grains having grain sizes sufficiently large so as to provide a substantially scratch-free surface upon polishing in a subsequent chemical mechanical polishing step.

Soft metal conductor

Method of making a soft metal conductor

A method of filling high aspect ratio vias and lines on the upper surface of a substrate prevents voids from being formed therein. The method comprises the steps of filling the lines and vias by surface diffusion at room temperature and at a pressure of 1 Torr. Step coverage of the fill material and sputtering parameters are chosen to satisfy a predetermined relationship. The upper surface of the substrate comprises regions of exposed aluminum, aluminum-copper or copper alloys. After filling the vias and lines, the exposed aluminum, aluminum-copper or copper alloys are reacted with a gas containing germanium to form a germanium alloy over the upper surface of the substrate.

High aspect ratio low resistivity lines/vias by surface diffusion

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6, can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

Method for fabricating high aspect ratio low resistivity lines/vias by

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap of W.sub.x Ge.sub.y. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Production of substrate for tensilely strained semiconductor

A structure and method for fabricating circuits which use field effect transistors (FETs), bipolar transistors, or BiCMOS (combined Bipolar/Complementary Metal Oxide Silicon structures), uses low temperature germanium gas flow to affect metals and alloys deposited in high aspect ratio structures including lines and vias. By using a germanium gas flow, germanium (Ge) will be introduced in a surface reaction which prevents voids and side seams and which also provides a passivating layer of CuGe. If a hard cap is needed for surface passivation or a wear-resistance application, the GeH.sub.4 gas followed by WF.sub.6 can be used to produce an in-situ hard cap and polish stop of W.sub.x Ge.sub.y, a tungsten-germanium alloy. Further, high aspect ratio vias/lines (aspect ratio of 3 or more) can be filled by utilizing low pressures and high temperatures (i.e., below 450.degree. C.) without degrading the underlying metals.

High aspect ratio low resistivity lines/vias with a tungsten-germanium

A silicon quantum wire transistor. A silicon substrate is sub-etched leaving a thin ridge (.ltoreq.500 .ANG. tall by .ltoreq.500 .ANG. wide) of silicon a quantum wire, on the substrate surface. An FET may be formed from the quantum wire by depositing or growing gate oxide and depositing gate poly. After defining a gate, the source and drain are defined. Alternatively, an optically activated transistor is formed by defining an emitter and collector and providing a path for illumination to the wire.

One dimensional silicon quantum wire devices and the method of

A programmable antifuse element comprising adjacent bodies of germanium and aluminum or aluminum allow form a low resistance connection of good mechanical and thermal properties when heated to a temperature where alloying of the aluminum and germanium occurs. Heating for the purpose of programming the antifuse element can be done by electrical resistance heating in the-germanium, which may be doped to achieve a desired resistance value, or by laser irradiation. Due to the high resistance of intrinsic or lightly doped germanium, a resistance change ratio of greater than 10,000:1 is achieved.

Antifuse element with electrical or optical programming

A structure with strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

Substrate for tensilely strained semiconductor

The fabrication and use of corrosion resistant Cu/Cu(x)Ge(y) alloy or Cu/Cu.sub.3 Ge phase bilayer interconnect metal lines is disclosed. A solid state, selective process of forming a Cu.sub.3 Ge phase or Cu(x)Ge(y) alloy by reacting GeH.sub.4 gas with Cu surface at low pressure in CVD reactor at temperatures of 200.degree.-450.degree. C. is described. Corrosion resistant semiconductor devices and packaging interconnects where corrosion of copper interconnects was a problem, is now made possible by the Cu/Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy bilayer of the present invention. A structure where copper vias are completely or partially converted to Cu.sub.3 Ge or Cu.sub.x Ge.sub.y is presented. Also, dissimilar metals like Al--Cu can be connected by Cu.sub.3 Ge phase or Cu.sub.x Ge.sub.y alloy filled vias to improve electromigration performance.

Method of making corrosion resistant, low resistivity copper for

A capacitor is provided having a substrate and a first capacitor plate including a lattice mismatched crystalline material is formed over and supported by a surface of the substrate. A layer of insulating material is formed over and supported by the first capacitor plate. A second capacitor plate including a layer of conductive material is formed over and supported by the layer of insulating material.

Method for forming capacitors with roughened single crystal plates

A semiconductor light emitting/detecting device has a first doped silicon layer, an intrinsic silicon epitaxial layer formed on the first doped silicon layer, at least one quantum dot embedded within the intrinsic silicon epitaxial layer, and a second doped silicon layer formed on the second intrinsic silicon epitaxial layer.

Method of making semiconductor quantum dot light emitting/detecting

A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount. The stack is thereafter removed, wherein the combined TTV of the bonded substrate pair is further transferred and compressed a second compression amount into said epitaxial silicon layer, whereby said epitaxial silicon layer remains on said mechanical substrate to form the semiconductor layer of ultra-high thickness uniformity, the thickness uniformity being a controlled function of the first and second compression amounts.

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Yorktown Heights, NY, United States of America

Manu J Tejwani