Apple Inc.

Broadcom Corporation

Qualcomm Incorporated

Google Inc.

Manu Gulati

Timothy John Millet

Laurent Rene Moll

Erik P Machnicki

Gilbert H Herbeck

Barton Sano

Sukalpa Biswas

Michael F Culbert

Joseph Byron Rowlands

Brijesh Tripathi

Joshua P De Cesare

Shane J Keil

Anand Dalal

Jung Wook Cho

Gurjeet S Saund

Jeffrey R Wilcox

James B Keller

Cyril De La Cropte De Chanterac

Harshavardhan Kaushikkar

Michael J Smith

Shinye Shiu

Benjamin K Dodge

Koray Oner

James D Ramsay

Farid Nemati

Robert E Jeter

Shu-Yi Yu

Rakesh L Notani

Joseph Sokol, Jr

Bernard Joseph Semeria

Deniz Balkan

Rong Zhang Hu

Jason Rupert Redgrave

Keith Alan Cox

Albert Meixner

Alexei Elias Kosut

Parin Patel

Brian P Lilly

Josh P De Cesare

Arthur L Spence

Rohit Kumar Gupta

Kai Lun Hsiung

Lawrence John Madar, Iii

Keith Robert Pflederer

Kevin R Walker

Allan Douglas Knies

Fabien S Faure

Girault W Jones

Venkata Ramana Malladi

Munetoshi Fukami

Alon Naveh

Neeraj Parik

Kiran Kattel

Vinod Chamarty

Xiaoyu Ma

Hongil Yoon

Anubhav Mishra

Rahul Jagdish Thakur

Robert P Esser

Pulkit Desai

Weiping Liao

Yang Yang

Peter F Holland

Joseph P Bratt

Gerard Richard Williams

Timothy R Paaske

Wei-Han Lien

Gregory S Mathews

James D Kelly

James Vash

Srinivasa Rangan Sridharan

Per Hakan Hammarlund

Marc A Schaub

Christopher J Young

Michael Bekerman

Derek Fujio Iwamoto

Kevin C Wong

Wolfgang H Klingauf

Sagar Koorapati

Liang Deng

Christopher D Shuler

Nitin Makhija

Jianlin Yu

Jonathan Masters

Pradeep Kanapathipillai

Mitchell Palmer Lichtenberg, Jr

Tristan R Hudson

Suhas Kumar Suvarna Ramesh

Thomas H Huang

Thejasvi M Vijayaraj

Enming Zheng

Iii Lawrence Madar

A throttle management circuit is configured to receive throttle request(s) from at least one state detection circuit, generate and store a throttle recommendation in each clock cycle based on the received throttle request(s), and generate a throttle control signal to throttle activity of processing circuits based on a recent and stored throttle recommendation. The throttle requests may be based on measures of electric states, thermal states, and/or activity states among the processing circuits monitored by the LAM circuit and the measured states may be caused by activity of the processing circuits. The throttle management circuit can provide a local, dynamic, low-latency response to mitigate harm that could otherwise be caused by the measured local states of the processing circuits while waiting for a response from the power management hierarchy. In some examples, the throttle recommendation generated in each cycle affects the throttle control signal for a plurality of subsequent cycles.

Adaptive local throttle management of processing circuits based on detected states in an integrated circuit (IC) chip

In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

System on a chip with always-on processor

This application is directed to power management at a processor system having a plurality of domains. Power samples are collected from the domains and combined to generate a system temperature profile including a temporal sequence of system temperature values. When the system temperature profile satisfies a first criterion, it is determined in real time whether a respective system temperature value of the system temperature profile satisfies a second criterion or a third criterion. In accordance with a determination that the respective system temperature value satisfies the second criterion, a power management engine determines power budgets of the domains on a firmware level and enables operations of the domains according to the power budgets. In accordance with a determination that the respective system temperature value satisfies the third criterion, a subset of domains are selected to apply a respective power throttling action directly on a hardware level.

Dynamic power management for SoC-based electronic devices

In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Always-on audio control for mobile device

In an embodiment, a system on a chip (SOC) includes a component that remains powered when a central processing unit (CPU) processor and a memory controller of the SOC are powered off. The component may include a sensor capture unit to capture audio samples from an audio detector circuit and write them to a memory of the component. A processor of the component may be configured to search the audio samples for a predetermined pattern during a time when the CPU processor and the memory controller are powered down. In some embodiments, based on the audio samples filling to a threshold level in the memory of the component and a lack of detection of the predetermined pattern, the component is configured to wake up the memory controller and a path to the memory controller in order to write the audio sample to a memory controlled by the memory controller.

System on a chip with always-on component with powered-down configurations to process audio samples

An electronic system has a plurality of processing clusters including a first processing cluster. The first processing cluster further includes a plurality of processors and a power management processor. The power management processor obtains performance information about the plurality of processors, executes power instructions to transition a first processor of the plurality of processors from a first performance state to a second performance state different from the first performance state, and executes one or more debug instructions to perform debugging of a respective processor of the plurality of processors. The power instructions are executed in accordance with the obtained performance information and independently of respective performance states of other processors in the plurality of processors of the first processing cluster. In some implementations, the power management processor receives, from a system controller external to the plurality of processing clusters, a first power allocation for the first processing cluster.

Dynamic voltage and frequency scaling (DVFS) within processor clusters

An electronic system has a plurality of power domains, and each domain includes a subset of one or more processor clusters, first memory, PMIC, and second memory. A plurality of power sensors are distributed on the electronic system and configured to collect a plurality of power samples from the power domains. A power management engine is configured to process the power samples based on locations of the corresponding power sensors to generate one or more power profiles and a plurality of power throttling thresholds. The power manage engine is configured to implement a global power control operation by determining power budgets of the power domains on a firmware level and enabling operations of the power domains accordingly. The power manage engine is also configured to enable a plurality of local power control operations to be directly implemented on the power domains based on the power throttling thresholds.

Hierarchical power management architecture for SoC-based electronic devices

Methods, systems, and apparatus, for handling applications in an ambient computing system. One of the methods includes determining, by a low-power processing component, that particular sensor signals have a particular property. In response, a machine learning engine performs an inference pass over a machine learning model using the sensor signals to generate a model output. If the model output of the machine learning engine matches an application-specific condition, one or more of the other processing components are activated to execute an particular application corresponding to the application-specific condition.

Low-power ambient computing system with machine learning

In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

Unified addressable memory

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a system-level cache to allocate cache resources by a way-partitioning process. One of the methods includes maintaining a mapping between partitions and priority levels and allocating primary ways to respective enabled partitions in an order corresponding to the respective priority levels assigned to the enabled partitions.

Way partitioning for a system-level cache

Growing community of inventors

Saratoga, CA, United States of America

Manu Gulati