Intel Corporation

Merck Patent Gmbh

University of California

Lam Research Corporation

Ontrak Systems, Inc.

Mansour Moinpour

Reza M Golzarian

Alexander Tregub

Farhad K Moghadam

Michael D Goodner

Robert P Meagley

Wilbur C Krusell

John M deLarios

Mohsen Salek

Lynn S Ryle

Seiichi Morimoto

Young C Park

Donald E Anderson

Te Hua Lin

Tom Bramblett

Adrien Lavoie

Peer Kirsch

Boyan Boyanov

Grant M Kloster

Shintaro Arai

Andrew C Kummel

Hoang Viet Nguyen

Harsono S Simka

Juan E Dominguez

John J Plombon

Michael L McSwiney

Matthew J Prince

Glen N Wada

Henning Seim

Huey-Chiang Liou

Sebastian Resch

Marc Tornow

Itai Lieberman

Daniel Moser

S M Sadjadi

David Fryer

Takuya Kamiyama

Ravindra Kanjolia

Julian Dlugosch

Francis M Tambwe

Ken Schatz

Jan V Shubert

Yang-Chin Shih

S M Reza Sadjadi

Hoang T Nguyen

SeongUk Yun

Cheng-Hsuan Kuo

Victor K Souw

Alex Tregub

Gary Ding

Andrea C Oehler

Reza M c/o Intel Corporation Golzarian

The present invention relates to an electronic switching device comprising an organic molecular layer in contact with a metal nitride electrode for use in memory, sensors, field-effect transistors or Josephson junctions. More particularly, the invention is included in the field of random access non-volatile memristive memories (RRAM). The invention thus further relates to an electronic component comprising a crossbar array comprising a multitude of said electronic switching devices.

Electronic switching device

A method of forming a conformal layer including TiN in a via includes introducing a precursor into a reaction chamber according to a first exposure schedule. The precursor includes non-halogenated metal-organic titanium. The first exposure schedule indicates precursor exposure periods. Each precursor exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the precursor during the particular duration of time. The method includes introducing a co-reactant into the reaction chamber according to a second exposure schedule. The co-reactant includes nitrogen. The second exposure schedule indicates co-reactant exposure periods. Each co-reactant exposure period is associated with a particular duration of time and a particular duty cycle over which to introduce the co-reactant during the particular duration of time. The method includes providing the conformal layer including TiN in the via based on said introducing the precursor and the co-reactant.

Methods of forming low resistivity titanium nitride thin film in horizontal vias and related devices

A method for depositing a high-k dielectric material on a semiconductor substrate is disclosed. The method includes applying a chemical bath to a surface of a substrate, rinsing the surface, applying a co-reactant bath to the surface of the substrate, and rinsing the surface. The chemical bath includes a metal precursor which includes at least a hafnium compound, an aluminium compound, a titanium compound, zirconium compound, a scandium compound, a yttrium compound or a lanthanide compound.

Deposition method for high-k dielectric materials

In a formulation of a wafer cleaning brush, forming a polymer solution with a plurality of nano-scale porogens or with a synthetic pore forming agent and curing the polymer solution to form a porous polymeric material.

Brush for cleaning wafer

A silicon nitride film may be deposited on a work piece using conventional deposition techniques and a selected source for use as a silicon precursor. A nitrogen precursor may also be selected for film deposition. Using the selected precursor(s), the temperature for deposition may be 500&#xb0; C., or less.

Forming a silicon nitride film

A method of forming and a device including an interconnect structure having a unidirectional electrical conductive material is described. The unidirectional conductive material may overlie interconnect materials, and/or may surround interconnect materials, such as by lining the walls and base of a trench and via. The unidirectional conductive material may be configured to conduct electricity in a direction corresponding to a projection to or from a contact point and conductive material overlying the unidirectional conductive material, but have no substantial electrical conductivity in other directions. Moreover, the unidirectional conductive material may be electrically conductive in a direction normal to a surface over which it is formed or in directions along or across a plane, but have no substantial electrical conductivity in other directions. Finally, the unidirectional conductive material may have properties tending to reduce metal diffusion, reduce electron migration, provide adhesion or bonding, and/or act as an etch stop.

Unidirectionally conductive materials for interconnection

A method for detecting particle agglomeration in CMP slurries. In accordance with an implementation of the invention, a CMP slurry is tested for abrasive particle agglomeration by applying an ultra high shearing force to the slurry and analyzing its rheological behavior. Through the comparison of slurry rheological behavior, implementations of the invention make it possible to detect particle agglomeration in a slurry and to distinguish between fresh and aged slurries.

Detecting particle agglomeration in chemical mechanical polishing slurries

An organic-framework zeolite interlayer dielectric is disclosed. The interlayer dielectric's resistance to chemical attack, its dielectric constant, its mechanical strength, or combinations thereof can be tailored by (1) varying the ratio of carbon-to-oxygen in the organic-framework zeolite, (2) by including tetravalent atoms other than silicon at tetrahedral sites in the organic-framework zeolite, or (3) by including combinations of pentavalent/trivalent atoms at tetrahedral sites in the organic-framework zeolite.

Organic-framework zeolite interlayer dielectrics

The present invention relates to the manufacture and use of novel pre-coated abrasive particles and particle slurries for the chemical mechanical polishing (CMP) of semiconductor wafers, thin films, inter-layer dielectric, metals, and other components during integrated circuit, flat panel display, or MEMS manufacturing. For example, polishing slurry abrasive particles can be pre-coated with additives, such as, inhibitors and/or surfactants during manufacture of the abrasive particles or slurry. The additive's opportunity to react directly with the abrasive particles early in the particle manufacturing process provides a slurry having a more stable, selectable, and predictable ratio of abrasive particles pre-coated with a more stable, selectable, and predictable amount and type of additives.

Pre-coated particles for chemical mechanical polishing

A multi-platen, multi-slurry chemical mechanical polishing method comprises providing a substrate having a surface that includes at least one nitride structure and an oxide layer atop the nitride structure, performing a first CMP process on the substrate using a first platen with a silica based slurry to remove a bulk portion of the oxide layer without exposing the nitride structure, performing a second CMP process on the substrate using a second platen with a ceria based slurry to remove a residual portion of the oxide layer and to expose at least a portion of the nitride structure, and performing a third CMP process on the substrate using the first platen with a silica based slurry to remove at least one defect caused by the ceria based slurry.

Multi-platen multi-slurry chemical mechanical polishing process

In one embodiment, a CMP pad is conditioned by repeatedly cycling the CMP pad between a first temperature and a second temperature higher than the first temperature to eliminate at least one crystalline area in the CMP pad.

Conditioning polishing pad for chemical-mechanical polishing

Thermally analysis of layers and multiple layer structures used in the semiconductor processing arts is disclosed. A modulated calorimetric analysis may be used to determine a thermal signature that characterizes the chemical properties of a sample of material. The signature may include one or more thermal properties such as heat capacities. The signature may be used to compare and infer the suitability of a material for use in an integrated circuit manufacturing process. A thermal signature for a material that is not known to be suitable for manufacturing integrated circuits may be compared with a thermal signature for a standard material that is known to be suitable in order to determine whether the aforementioned material is suitable. Multiple layer structures may also be analyzed, compared, and inferred, and approaches for determining thermal signatures for any individual layer of the multiple layer structure are disclosed.

Thermal analysis and characterization of layers and multiple layer structures

An apparatus for conditioning a polishing pad of a CMP apparatus for making semiconductor wafers is provided which includes a control arm configured to extend at least partially over a polishing pad. The apparatus also includes at least one cylindrical conditioning piece coupled to the control arm where the control arm is configured to apply the at least one cylindrical conditioning piece to the polishing pad.

Polishing pad conditioning

Embodiments of methods and apparatus in accordance with the present invention provide a chemical mechanical planarization (CMP) process that provides single or multiple polishing pads to have a different rotational velocity, applied pressure and oscillation frequency on the surface of the substrate to address and compensate for the WIW (with-in-substrate) and WID (with-in-die) non-uniformities in planarization ability. The velocity of each polishing pad is adjustable providing a closer match to the substrate surface velocity over a particular zone to yield a linear velocity on the surface of the substrate.

Surface planarization

Growing community of inventors

San Jose, CA, United States of America

Mansour Moinpour