Apple Inc.

Nvidia Corporation

Alvand Technologies, Inc.

Integrated Device Technology, Inc.

Alvand Technology, Inc.

Mansour Keramat

Mehrdad Heshami

Seyedeh Sedigheh Hashemi

Edward Wai Yeung Liu

Timothy C Kuo

Ali Mesgarani

Dusan Stepanovic

Vahid Majidzadeh Bafar

Tao Liu

Soheil Golara

Vijay Srinivas

Yi Chun A Fu

Syed S Islam

Tao Wang

Yuan-Ju Chao

Hyunsik Park

Ashirwad Bahukhandi

Ke Yun

KiYoung Nam

Bruno Werner Garlepp

Jafar Savoj

Emerson S Fang

Farzan Farbiz

Fabien S Faure

Ali Tabatabaei

Arnaud J Forestier

Friedel Gerfers

Brian Liebowitz

Nick Chang

Denis C Daly

Sechang Oh

Hamid Nejati

Sudharsan Kanagaraj

Albert Hsu Ting Chang

Ahmed Mohamed Abdelatty Ali

Mahdi Khoshgard

Ahmad Al Marashli

Jasdeep S Dhaliwal

Si Chen

Bo Liang

Douglas J Hogberg

Feng Bao

Ali Agah

Keivan Etessam Yazdani

Ali Meaamar

Ashkan Borna

Sedigheh Hashemi

Adaptive calibration of analog front-end and receiver non-idealities is disclosed. An analog front-end (AFE) circuit is configured to receive an analog input signal, and includes an analog signal path having one or more analog circuits. A test signal generator inputs an analog test signal into the analog signal path. The AFE circuit combines analog input signal and the test signal and generates, using one or more analog circuits in the analog signal path, an analog output signal based on the analog input signal combined with the analog test signal. A digital signal processing (DSP) circuit processes a digital input value that corresponds to the analog output signal, and performs calibrations of respective parameters of the one or more analog circuits. To perform the calibrations, the DSP circuit is configured to separate a digital representation of the analog test signal from a remainder of the digital value.

Adaptive calibration of analog front end and receiver non-idealities

The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.

Data converter with offset tone reduction

A voltage reference circuit included in a computer system includes an asymmetric amplifier circuit that includes two metal-oxide semiconductor field-effect transistors with different threshold voltages. The voltage reference circuit also includes an output circuit that generates, using a control signal, a bias signal and an output current that is used by a divider circuit to generate a reference voltage and a feedback voltage. The reference voltage and bias signal are used by the amplifier circuit to generate the control signal, which is based on a difference between the transistors' threshold voltages.

Voltage reference circuit

A power detect circuit is disclosed. A power detect circuit includes a voltage multiplier that receives an external supply voltage and generates a second supply voltage that is greater than the former. A voltage regulator is coupled to receive the second supply voltage and outputs a regulated supply voltage. A bandgap circuit is coupled to receive the second supply voltage when a first switch is closed, and the regulated supply voltage when a second switch is closed. The bandgap circuit generates a reference voltage for the voltage regulator, as well as one or more output voltages. A comparator circuit is coupled to receive the one or more output voltages from the bandgap circuit, and may compare these one or more output voltages to the regulated supply voltage.

Low voltage high precision power detect circuit with enhanced power supply rejection ratio

A reference generator circuit included in a computer system may employ multiple field-effect transistors to generate a reference voltage whose value is based on the threshold voltages of the multiple field-effect transistors. The reference generator circuit can include a current source that generates a bias current. One of more stages included in the reference generator circuit can generate, using the bias current, respective output voltages whose values are based on differences in threshold voltages of field-effect transistors included in the stages. The output voltages can be combined to generate different reference voltage values.

Low-voltage power supply reference generator circuit

The present disclosure is directed to a system implementing a sensor. A sensing system is implemented in a functional circuit block that is coupled to a global supply voltage node. The sensing system includes a power converter circuit configured to generate a regulated voltage level on a local supply node using the voltage present on the global supply voltage node. The system also includes a sensor circuit coupled to receive the regulated voltage node, wherein the sensor is configured to compare corresponding parameters of different ones of a number of subset of device at a plurality of different time points and generate a plurality of comparison results. The comparisons generate an analog signal that is proportional to the operating parameter. An analog-to-digital converter (ADC) is coupled to receive the analog signal and generate a plurality of bits corresponding thereto.

Micro analog sensor circuit and system

A sensor system included in an integrated circuit includes multiple sensor circuits and a control circuit. Using characterization data, a model may be generated that defines a relationship between measurable parameters of the integrated circuit and an operating characteristic of the integrated circuit. The control circuit can combine, using a function included in the model, data from the multiple sensor circuits to determine a value of the operating characteristic that is more accurate than a sensor circuit configured to measure a single parameter of the integrated circuit that varies with the operating characteristic.

Process-insensitive sensor circuit

A voltage monitoring circuit is disclosed. An apparatus includes a first physical interface circuit and a real-time oscilloscope circuit configured to monitor a first voltage provided to the first physical interface circuit. The real-time oscilloscope is configured to receive an indication that an error was detected in data transmitted from the first physical interface to a second physical interface circuit. The real-time oscilloscope is further configured to provide for debug, to a host computer external to the first interface, information indicating a state of the first voltage at a time at which the error was detected.

Voltage monitoring circuit for interface

Systems, apparatuses, and methods for performing digital pre-distortion compensation of digital-to-analog converter non-linearity are described. A correction circuit receives a digital input word and couples a portion of the most significant bits (MSB's) of the digital input word to a correction lookup table (LUT). A correction value is retrieved from a correction LUT entry that matches the MSB's of the digital input word. Next, the correction value is added to the original digital input word in the digital domain. Then, the sum generated by adding the correction value to the original digital input word is optionally clipped if the sum exceeds the DAC core's input range. Next, the DAC core converts the sum into an analog value that is representative of the digital input word. The above approach helps to reduce non-linearities introduced by the DAC core in an energy-efficient manner by performing a correction in the digital domain.

Digital pre-distortion compensation of digital-to-analog converter non-linearity

A power supply circuit included in a computer system regulates a power supply voltage using an input power supply. During startup, the power supply circuit uses a first reference voltage that is generated using the input power supply to regulated the power supply voltage. After a period of time has elapsed, the power supply circuit switches to using a more accurate second reference voltage that is generated using the regulated power supply voltage.

Analog supply generation using low-voltage digital supply

Systems, apparatuses, and methods for performing hybrid non-linearity correction for a digital-to-analog converter (DAC) are described. A circuit includes two correction LUTs, an edge-trim DAC, and a DAC core. A lookup of a first correction LUT is performed using a portion of the most significant bits (MSBs) of a received digital input value. A first correction value, retrieved from the first correction LUT, is applied to the digital input value to generate a corrected value. The corrected value is provided to the DAC core and to a second correction LUT. A second correction value, retrieved from the second correction LUT, is compared to the first correction value. If the second correction value is different from the first correction value, the difference is provided to the edge-trim DAC to generate an analog correction which is applied to an analog output of the DAC core.

Hybrid digital-to-analog converter non-linearity calibration

A comparator circuit included in a computer system employs an inverter circuit as a high-speed comparison circuit. To allow the inverter circuit to compare an input signal to a particular threshold value, a trip point of the inverter circuit is adjusted to match the threshold value by modifying a voltage level of a power supply node coupled to the inverter. To modify the voltage level of the power supply node, a replica of the inverter circuit is biased to generate a bias signal that corresponds to the trip point of the inverter circuit. A comparator circuit compares the bias signal to the threshold value, and adjusts the voltage level of the power supply node using results of the comparison. An output circuit adjusts an output of the inverter circuit to generate a full-rail output signal.

High-precision and high-bandwidth comparator

A power supply circuit included in a computer system is configured to generate a particular voltage level on a regulated power supply node using multiple charge pump circuits coupled together via a regulation device to provide regulation. A first charge pump circuit is configured to, using a voltage of an input power supply node, generate an intermediate voltage level, which is regulated by the regulation device. The second charge pump is configured to generate a voltage level on the regulated power supply node using a regulated version of intermediate voltage level. An impedance of the regulation device is adjusted using results of comparing the voltage level of the regulated power supply node to a reference voltage.

An image sensing system and methods for operating the same are disclosed. An image sensing system includes a plurality of pixel circuits, a multiplexer configured to select one of the pixel circuit and provide analog pixel data without sampling, and a successive approximation register (SAR) analog-to-digital converter (ADC) configured to convert the analog pixel data into digital data. The SAR ADC includes a capacitive digital-to-analog converter (CDAC) configured to convert contents of the SAR into a corresponding analog signal for comparison, by a comparator, with the analog pixel data. The CDAC includes a two-dimensional array of circuit elements. A control circuit in the image sensing system is configured to cause random ones of the circuit elements of the CDAC to be selected for generation of the corresponding analog signal and add a dithering signal so a CDAC output and shuffle a multiplexer switch sequence to improve fixed pattern noise.

Low noise image sensor system with reduced fixed pattern noise

Growing community of inventors

San Jose, CA, United States of America

Mansour Keramat