Atheros Communications, Inc.

Atmosic Technologies Inc.

The Connectivity Patent Trust

Qualcomm Incorporated

Qualcomm Atheros Inc.

Manolis Terrovitis

David Kuochieh Su

David J Weber

Masoud Zargari

William John McFarland

Michael Peter Mack

John S Thomson

Arie Shor

Jason Chih-way Hou

Masoud Zaragari

Teresa Huai-Ying Meng

Srenik Suresh Mehta

Keith K Onodera

Keith Onedera

Method and apparatus for wirelessly transmitting and receiving power between devices are provided. A first device may convert power into RF energy and transmit the RF energy to a second device. In some implementations, the first device may steer the RF energy using beamforming techniques to the second device. The second device may receive and convert the RF energy into power for the second device. In some implementations, the second device may be powered solely or in part by power transmitted by the first device. In some implementations, the first device may include two or more RF energy harvesters and a power combiner. The power combiner may combine power from the two or more RF energy harvesters to power the second device and/or charge a battery.

Method and apparatus for wireless transmission and reception of power

Method and apparatus for controlling the power consumption of a wireless device are provided. A wireless device may include a configurable radio frequency (RF) front-end that may be configured to use fewer hardware stages and/or processing steps to reduce power consumption based at least in part on a signal quality, detected interference, or system information associated with a received RF signal. In some implementations, the configurable RF front-end may be configured to consume less power while receiving strong RF signals and configured to consume more power while receiving weak RF signals.

Method and apparatus for controlling power dissipation in a wireless receiver

Method and apparatus for generating and receiving a paging signal are provided. The paging signal may be received by a wireless device in a low-power state. The paging signal may include a target identification (ID) that may be associated with the wireless device. If the target ID is associated with the wireless device, the wireless device may leave the low-power state, enter an active power state and communicate with other wireless devices. The wireless device may include power harvesting circuitry to convert RF energy from the paging signal into power to operate a portion of the wireless device.

Wireless paging mode for low-power operation

Magnetic coupling of noise sources can have a negative impact on the net performance of sensitive circuits. A magnetic shielding loop can advantageously minimize magnetic coupling associated with a circuit on an integrated circuit (IC) by including on-chip components, off-chip components, and interface components connecting the on-chip and off-chip components. The components can include conductive paths and contact pads on a die, package, and printed circuit board. The magnetic shielding loop magnetically isolates at least one of input terminals and noise-generating elements of the circuit.

On-chip/off-chip magnetic shielding loop

Redundancies of power amplifiers (PAs) or low noise amplifiers (LNAs) at the front end of an RF device are used to reduce losses that typically occur at a diversity switch. A signal designator can advantageously be used to select designated signals, which are provided to the PAs for transmitting or provided by the LNAs during receiving.

Apparatus for signal power loss reduction in RF communication systems

Multiple power amplifiers in an RF front end are coupled to multiple antennas without diversity switching between the PAs and antennas. Diversity switches direct signals to broadcast by a selected antenna to a PA coupled to the selected antenna. Multiple LNAs are similarly coupled to the diverse antennas. Having one PA and LNA set for each antenna removes the need for diversity switching between the PA/LNAs and each antenna improving signal reception. In one embodiment, a single external PA performs broadcast functions and plural on-chip LNAs are used for reception. In another embodiment, phase shifters are coupled to each PA and LNA, which provide beam forming capability for broadcasts, and in phase signal combinations for received signals.

Method and apparatus for signal power loss reduction in RF communication systems

A complementary metal oxide semiconductor transceiver analog front end circuit includes a combined transmit and receive amplifier block that produces an amplified transmit differential signal and receives a receive differential signal through the same pair of input/output nodes coupled to an external network through an RF choke block. In one embodiment the combined transmit and receive amplifier block includes separate power amplifier and low noise amplifier circuits, while a second embodiment includes a power amplification stage and a combined power amplification/low noise amplification stage. The amplifier circuits may be constructed using a combination of thin oxide core transistors and thick oxide input/output transistors. DC feeds may be selected to power the circuits in response to a transmit/receive control signal. Bias voltages to the amplifier circuits' transistors may also be set in response to the transmit/receive control signal.

CMOS transceiver analog front end having a combined power amplifier and low noise amplifier

A dual band radio is constructed using a primary and secondary transceiver. The primary transceiver is a complete radio that is operational in a stand alone configuration. The secondary transceiver is a not a complete radio and is configured to re-use components such as fine gain control and fine frequency stepping of the primary transceiver to produce operational frequencies of the secondary transceiver. The primary transceiver acts like an intermediate frequency device for the secondary transceiver. Switches are utilized to divert signals to/from the primary transceiver from/to the secondary transceiver. The switches are also configured to act as gain control devices. Antennas are selected using either wideband or narrowband antenna switches that are configured as a diode bridge having high impedance at operational frequencies on control lines that bias the diodes.

Dual frequency band wireless LAN

An amplifier with linearization feedback includes an amplification stage that receives a feedback control signal from an envelope detection feedback network. The envelope detection feedback network controls the gain of the amplification stage based on an envelope of an input signal of the amplification stage, an envelope of an attenuated version of an amplified output signal of the amplification stage, and an offset adjustment signal generated by an offset calibration block. The envelope detection feedback network can include single stage or multiple stage envelope detectors. The amplification stage can include multiple, serially connected amplifiers. The gain of at least one amplifier in the amplification stage may be controlled by the feedback control signal. Additionally, the gain of some of the amplifiers in the amplification stage may be controlled digitally by gain adjustment signals based on comparing the feedback control signal to one or more reference signals.

System for amplifier linearization with envelope feedback

A differential circuit layout can advantageously use step symmetry for inductors and mirror symmetry for the rest of the circuit. Interconnect segments can be used to connect the terminals of the inductors to other components in the circuit. These interconnect segments facilitate the transition from the step symmetry of the inductors to the mirror symmetry of the other components. To provide this transition, the terminals of an inductor and its associated interconnect segments are formed on a middle axis of the inductor. This mixed symmetry can advantageously cancel the common-mode magnetic field, reduce the parasitic inductor coupling, and balance parasitic wiring capacitances between the two sides of the differential circuit.

Method of generating a layout for a differential circuit

An amplifier can advantageously use a power supply voltage source that provides a voltage greater than all breakdown voltages of the process associated with transistors of the amplifier. Specifically, cascoded configurations can be used to reduce the gate-drain and source-drain voltages of 'at-risk' transistors in the amplifier. During a power down mode, a bias shunt of the amplifier can isolate certain nodes from the voltage sources. At the same time, a charge circuit of the amplifier can charge those nodes to a predetermined voltage, thereby minimizing stress to the at-risk transistors during the power down mode. A multi-flavor power down signal generator circuit can advantageously generate the appropriate power down signals for driving various transistors of the amplifier during the power down mode.

Amplifier capable of using a power supply voltage higher than its process voltages

An RF amplifier can include multiple gain stages, wherein each gain stage can be DC coupled to an adjacent gain stage. Each input gain stage can include either n-type gain transistors or p-type gain transistors. Multiple input gain stages can be designed/built by interleaving input gain stages of different types. Notably, an input gain stage including n-type gain transistors has a p-type bias transistor. Similarly, an input gain stage including p-type gain transistors has an n-type bias transistor. In this configuration, the bias transistor is the same type as the downstream gain transistors. Therefore, each bias transistor can accurately track the behavior of the transconductance devices of the next gain stage.

DC-couples RF multi-stage amplifier

A peak detector can advantageously increase its bandwidth, i.e. its charging and discharging speed, while minimizing the ripple of its output signal by sensing the charging current of a storage device. In response to that charging current, the peak detector can control a discharge current, thereby accelerating its response. For example, the peak detector can reduce a discharge current in response to an increased charging current (which indicates a charging phase) and increase the discharge current in response to a decreased charging current (which indicates a discharge phase).

Technique to increase the speed of a peak detector

A phase selector for selecting a differential output is provided. The phase selector can include two matched transistor circuits. A first transistor circuit can receive a first differential input signal whereas a second transistor circuit can receive a second differential input signal. One of the transistor circuits can be used to dump an output current generated by the first differential input signal to Vdd. The other transistor circuit can be used to steer an output current generated by the second differential input signal to two output lines, thereby providing a differential output signal on the output lines.

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Berkeley, CA, United States of America

Manolis Terrovitis