Qualcomm Incorporated

Manokanthan Somasundaram

Jason Edward Podaima

Bohuslav Rychlik

Paul Christopher John Wiercienski

Kun Xu

Jaya Prakash Subramaniam Ganasan

Serag Gadelrab

Meghal Varia

Thomas Zeng

Dipti Ranjan Pal

Steven Halter

Kyle Ernewein

Carlos Javier Moreira

Christophe Avoinne

Alexander Miretsky

Sina Dena

Muhammad Umar Choudry

Myil Ramkumar

Jaya Subramaniam Ganasan

Christophe Denis Bernard Avoinne

Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks

Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.

Multi-threaded translation and transaction re-ordering for memory management units

Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM message interceptors may be positioned in various locations within a DVM network of a computing device so that DVM messages may be intercepted before reaching certain DVM destinations. A DVM message interceptor may receive a broadcast DVM message from first DVM source. The DVM message interceptor may determine whether a preemptive DVM message response should be returned to the DVM source on behalf of the DVM destination. When certain criteria are met, the DVM message interceptor may generate a preemptive DVM message response to the broadcast DVM message, and send the preemptive DVM message response to the DVM source.

Interconnect distributed virtual memory (DVM) message preemptive responding

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Markham, Canada

Manokanthan Somasundaram