Broadcom Corporation

Manoj Vajhallya

R Lakshmikanth Pai

Sandeep Bhatia

Gaurav Aggarwal

Girish Raghunath Hulmani

Vijayanand Aralaguppe

Aniruddha Sane

Chhavi Kishore

Bhaskar Mala Sherigar

Ravindra Bidnur

Himakiran Kodihalli

Ramadas Lakshmikanth Pai

Sivagururaman Mahadevan

An Inverse Transform (IT) conforming to MPEG AVC I_PCM that offers better video image quality than the MPEG-2/H.263 based video decoders and real time motion picture processing at 30 frames/seconds is described. The IT module performs 4&#xd7;4 Inverse Integer transform for AVC for MPEG-2 operations on a given macro block (MB) and all its sub blocks. The IT is the third module in the data flow pipeline of a video decoder, the first two being a variable length decoder (VLD) and an inverse quantizer (IQ). The IT module gets its inputs from IQ module and feeds its processed output to a Motion compensation unit/intra-prediction (MCU-IP) module, thus reconstructing the video picture.

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An interrupt sensitive extract byte instruction scheme is presented herein. The interrupt sensitive extract by instruction extracts bytes from data, depending on the presence of an interrupt. The extract byte instruction extracts bytes from data in the absence of the interrupt and does not extract bytes in the presence of the interrupt. The interrupt can be triggered by a set of counters that count the number of extracted bytes. By loading the counters with a particular number, the interrupt can be generated when the particular number of data bytes is extracted.

MPEG smart video transport processor with different transport packet handling

A system, method, and apparatus for dynamically booting processor code memory with a wait instruction is presented herein. A wait instruction precedes the transfer of a new code portion to the code memory. The wait instruction causes the processor to temporarily cease using the code memory. When the processor ceases using the code memory, the processor signals a direct memory access (DMA) module to transfer a new code portion to the code memory. The DMA module transfers the new code portion to the code memory and transmits a signal to the processor when the transfer is completed. The signal causes the processor to resume. When the processor resumes, the processor begins executing the instructions at the next code address.

Integrated circuit with DMA module for loading portions of code to a code memory for execution by a host processor that controls a video decoder

Presented herein is a direct memory access engine for providing data words in the reverse order. The data words are fetched in batches comprising a predetermined number of data words starting from the last data word and proceeding to the first data word. The batches are stored in a local buffer. The contents of the local buffer are transmitted in reverse order.

DMA engine for fetching words in reverse order

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Bengaluru, India

Manoj Vajhallya