International Business Machines Corporation

Cisco Technology, Inc.

Indian Oil Corporation Limited

Uop Lcc

Genencor International, Inc.

Danisco US Inc.

Samsung Electronics Co., Ltd.

Oracle International Corporation

Stmicroelectronics Pvt. Ltd.

Global Elmeast Inc.

General Electric Company

Dow Corning Corporation

Ranbaxy Laboratories, Inc.

Vlaamse Instelling Voor Technologisch Onderzoek N.v. (vito)

Danisco A/s, Genencor Division

Manoj N Kumar

Pratap Chandra Pattnaik

Jose Eduardo Moreira

Kattamuri Ekanadham

David Jones Craft

Prashant Anand

Janet Elizabeth Adkins

Manigandan Boopalan

Sudhir Kayamkulangara

Dinuraj K

Sankara Sri Venkata Ramakumar

Suresh Kumar Puri

Joon Chang

David James Shecterle

Mauricio J Serrano

Ravinder Kumar Malhotra

Prakash Chandra Sahoo

Fernando Valle

Joefon Jann

Ilie G Tanase

Grover Herbert Neuman

William Pettit Horn

Murthy V Devarakonda

Nikolai A Joukov

Hao Yu

Konstantinos Magoutis

Chung-Sheng Li

Birgit Monika Pfitzmann

George McNeil Lattimore

Ayrookaran J Poulose

Norbert George Vogl

Gokul Bhargava Kandiraju

Huaming Wang

Alain Charles Azagury

Ninad S Palsule

Anurag Ateet Gupta

William Albert Cuevas

Silvia Melitta Mueller

Dieter F Wendel

Zafar Ali

Daniel Manuel Dias

Deepak Kumar Tuli

Michael Kevin Ciraula

Debapriya Chatterjee

Niels Fricke

Amitoj Singh

Robert Douglas Cryer

M Harunur Rashid

Dung Q Nguyen

Peter G Schultz

Arun Kwangil Iyengar

Brian William Thompto

Manish Satyapal Gupta

Eric Albin Voit

Stephen W Sohn

Mukesh Kumar Mohania

Biplav Srivastava

Wlodek Wlodzimierz Zadrozny

Amit Anil Nanavati

Shwetha Subray Bhandari

Yuan-Chi Chang

Maarten Jakob Boersma

Suresh Kumar Batchu

Jayarama K Shetty

Krishna Kummamuru

Peichun Peter Liu

Asit Dan

Gregory A Funk

Gregory Marshall Whited

Katherine D Collier

Gregg Alan Wilson

Gopal K Chotani

Sanjiv Kumar Mazumdar

Mark Paul Lapinski

Raghuram Krishnapuram

Kiyoshi Maruyama

Abhishek Jain

Junko Tamiya

Biswapriya Das

Karl John Sanford

Sujal Sheth

Ravi Prakash Gupta

Gabriele Maria Galimberti

Upendra Sharma

Natwar Modani

Arun Theebaprakasam

Kiran Ladkat

Parul Alok Mittal

Philip George Shephard, Iii

Vishal Singh Batra

Pavan Sudheendra

Hari S Bajpai

Nilesh P Junnarkar

Jack Lawrence Kouloheris

Shane Robert Vermette

Jeff P Pucci

Terry Lee Leasure

Yeong-Chang L Lien

Friedrich C Wernicke

Rajinder Paul Singh

A processor includes a register file and an execution unit. The execution unit includes a hash circuit including at least a state register, a state update circuit coupled to the state register, and a control circuit. Based on a hash instruction, the hash circuit receives from the register file and buffers within the state register a current state of a message being hashed. The state update circuit performs state update function on contents of the state register, where performing the state update function includes performing a plurality of iterative rounds of processing on contents of the state register and returning a result of each of the plurality of iterative rounds of processing to the state register. Following completion of all of the plurality of iterative rounds of processing, the execution unit stores contents of the state register to the register file as an updated state of the message.

Hardware-based implementation of secure hash algorithms

A processor includes an execution unit for executing a message padding instruction including an operand field indicating a register buffering a message block segment of a message block to be padded and a mode field indicating which hash functions is to be applied to the message block. The execution unit includes a padding circuit configured to receive a message block segment from a register indicated by the operand field, where the message block spans multiple registers in a register file. Based on which hash function is indicated by the mode field, the padding circuit selects a byte location in the message block segment at which to insert at least one padding byte and inserts the at least one padding byte at the byte location within the message block segment. The message block segment as padded by the at least one padding byte is written back to the register file.

Hardware-based message block padding for hash algorithms

Methods are presented herein for a reduced state machine that describes nodes and relationship dynamics representing real network elements (networking devices and software processes) in a computer/data network, and abstracted logical items. Logical states of networking features of the network elements are reflected in the graph, while configuration data is stored for completeness. A method called a 'Versioner Algorithm' is provided to record the temporal history of a node and its state over time within the node's metadata itself, while recorded relationships represent logical relations between observed nodes. A method is also provided to time-travel back to observe a historical view of the network. Further still, a method is provided to a difference of two historical topologies and return that data in human-readable or machine consumable form.

Methods for implementing time-travelling networks using extensions to graph databases

Aspects of the present disclosure relate to encrypted data processing (EDAP). Encrypted data from a cache to be loaded into a register file can be accessed. The encrypted data can be decrypted to receive cleartext data. The cleartext data can be written to the register file. The cleartext data can be processed using at least one functional unit to receive cleartext computation results. The cleartext computation results can then be written back to the register file.

Encrypted data processing design including cleartext register files

A system may determine that two instructions may be combined based on a processing power of the processor and a size of the instructions, fuse the two instructions into a pair, map the two instructions with a single register tag, write the register tag into a mapper with bits indicating that the register tag is for a first instruction of the two instructions, write the register tag into the mapper with bits indicating that the register tag is for a second instruction of the two instructions, write the fused instruction pair into an issue queue, issue the fused instruction pair to a vector-scalar transformation units (VSU), and execute the two instructions.

Loosely-coupled slice target file data

Aspects of the present disclosure relate to encrypted data processing (EDAP). A processor includes a register file configured to store ciphertext data, an instruction fetch and decode unit configured to fetch and decode instructions, and a functional unit configured to process the stored ciphertext data. The functional unit further includes a decryption module configured to decrypt ciphertext data from the register file to receive cleartext data using an encryption key stored within the functional unit. The functional unit further includes a local buffer configured to store the cleartext data. The functional unit further includes an arithmetic logical unit configured to generate cleartext computation results using the cleartext data The functional unit further includes an encryption module configured to encrypt the cleartext computation results to generate ciphertext computation results for storage back into the register file.

Encrypted data processing design including local buffers

Embodiments for providing memory access operations for graph analytics by a processor are disclosed. An entire chunk of load and store instructions may be atomically and concurrently executed, where the entire chunk of the load and store instructions are delineated from a plurality of alternative load and store instructions.

Memory access operations for large graph analytics

In a fronthaul network system, when a CPRI link fault is detected at either of the REC or RE, both the REC and RE perform a Layer 1 synchronization. The fault may be a loss of signal, loss of frame, or a line code violation, which also translates to a loss of signal if seen beyond a threshold. A proxy slave recognizes the fault in a CPRI signal from a first radio device and inserts the fault alarm into a header of a radio over Ethernet frame. The proxy slave continues to communicate the signal for a configured number of hyper-frames. A proxy master receives the signal and communicates the signal and the fault alarm to a receiving radio device for a configured number of hyper-frames. The proxy and radio devices all perform a joint resynchronization.

Link fault handling in fronthaul communication networks

A hydrocarbon isomerization system for an iC4 feed stream that provides for removal of C3s from an isomerization reactor feed stream by the addition of a depropanizer column to remove C3s from the reactor effluent stream after it has passed through a stabilizer column. This configuration prevents a buildup of C3s in the system and provides significant savings by reducing the size of the chloride treaters that are used to remove chlorides from off gas, increasing chlorides recovered to the hydrocarbon feed stream for use in combination with the isomerization catalyst. Significant utility savings are provided as well as a reduction in the amount of perchloroethane (PERC) and adsorbent that are required.

Isomerization process

The present invention relates to a booster composition for enhancing the biogas yield and stabilizing the operation of a biomethanation plant, a method for the preparation of said booster composition and a method for enhancing the biogas yield and stabilizing the operation of a biomethanation plant using said composition by ameliorating the effect of shock conditions like pH and temperature. The booster composition comprises of specifically defined constituents selected from controlled release agents, redox potential balancers, direct interspecies electron transfer (DIET) improvers, micronutrient balancers, and Co-factors.

Booster composition to improve biogas yield and to stabilize the digester performance

The present disclosure is directed to seamless access to a common physical disk in an AMP system without an external hypervisor, and includes one or more processors and one or more computer-readable non-transitory storage media comprising instructions that, when executed by the one or more processors, cause one or more components of the system to perform operations including instantiating, by a first instance, a second instance during a system upgrade, creating, in the first instance, a first disk abstraction for a block device of a physical disk, and attaching the block device under the first disk abstraction. The operations further include providing the second instance network-based access to the physical disk using the first disk abstraction of the first instance during the system upgrade.

Seamless access to a common physical disk in an AMP system without an external hypervisor

The present invention provides a composition and a method for mitigating formation or activity of a corrosion-associated biofilm on metal surfaces of pipelines. The pipelines are first treated with pigs i.e. bi-di pigs for removing/disturbing biofilm, followed by microbial treatment i.e. application of microbecidal composition. The microbecidal composition comprising at least one alcohol, one corrosion inhibitor, one surfactant, one biocide and a lignin-based nanoparticle. The lignin-based nano particle is functionalized with amine functionalizing agent. The present composition and method is eco-friendly, as low concentration is sufficient and further, regular dosing is not required for MIC control.

Microbecidal composition and a method for mitigating internal microbiological influenced corrosion in petroleum transporting pipelines

Techniques that provide link auto-negotiation between a radio equipment controller (REC) and a radio equipment (RE) are described herein. In one embodiment, a method includes performing, by a proxy master, a Common Public Radio Interface (CPRI) Layer 1 (L1) link auto-negotiation with a RE to achieve a L1 synchronization between the proxy master and the RE at a link bit rate; communicating the link bit rate from the proxy master to a proxy slave; performing, by the proxy slave, a CPRI L1 link auto-negotiation with a REC to determine whether a L1 synchronization between the proxy slave and the REC is achieved, wherein if the L1 synchronization is achieved, the link bit rate is a common matching link bit rate achieved; and upon the common matching link bit rate being achieved, establishing a CPRI link between the REC and the RE using the common matching link bit rate.

Link auto-negotiation between a radio equipment controller (REC) and radio equipment (RE) in an ethernet-based fronthaul network

A process increases the concentration of normal paraffins in a feed stream comprising separating a naphtha feed stream into a normal paraffin rich stream and a non-normal paraffin rich stream. A naphtha feed stream may be separated into a normal paraffin stream and a non-normal paraffin stream. An isomerization feed stream may be taken from the non-normal paraffin stream and isomerized over an isomerization catalyst to convert non-normal paraffins to normal paraffins and produce an isomerization effluent stream. The isomerization effluent stream may be separated into a propane stream and a C4+ hydrocarbon stream optionally in a single column. The C4+ hydrocarbon stream may be recycled to the step of separating a naphtha feed stream.

Process for increasing the concentration of normal hydrocarbons in a light naphtha stream

A Reduced Instruction Set Computer ('RISC') supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit ('CPU'), a set of operations are executed on a state of a special purpose execution unit (&#x201c;SPU&#x201d;) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

Supporting large-word operations in a reduced instruction set computer ('RISC') processor

Growing community of inventors

Austin, TX, United States of America

Manoj N Kumar