Intel Corporation

Conexant Systems, Inc.

Manoj Mehta

Ruban Kanapathippillai

Earle F Philhower, Iii

Siva Venkatraman

Kumar Ganapathy

Thu Nguyen

Kenneth Malich

Brett Bernath

John Milford Brooks

Yoav Pesach Goldenberg

Saurin Shah

Anurag Bist

Chris Lawton

Dianne L Steiger

A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

Method and apparatus for reconfigurable memory

Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

IC memory complex with controller for clusters of memory blocks I/O multiplexed using collar logic

An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.

Unified shared pipeline allowing deactivation of RISC/DSP units for power saving

Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.

Bus state keepers

One aspect of the invention relates to a messaging communication scheme for controlling, configuring, monitoring and communicating with a signal processor within a Voice Over Packet (VoP) subsystem without knowledge of the specific architecture of the signal processor. The messaging communication scheme may feature the transmission of control messages between a signal processor and a host processor. Each control message comprises a message header portion and a control header portion. The control header portion includes at least a catalog parameter that indicates a selected grouping of control messages and a code parameter that indicates a selected operation of the selected grouping.

System and method for controlling signal processing in a voice over packet (VoP) environment

In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.

Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus

A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Growing community of inventors

Laguna Hills, CA, United States of America

Manoj Mehta