Vanguard International Semiconductor Corporation

Manoj Kumar

Chia-Hao Lee

Chih-Cherng Liao

Pei-Heng Hung

Hsiung-Shih Chang

Jui-Chun Chang

Shang-Hui Tu

Jun-Wei Chen

Ankit Kumar

Priyono Tri Sulistyanto

Shin-Cheng Lin

Wen-Hsin Lin

Li-Che Chen

Chang-Xiang Hung

Rudy Octavius Sihombing

Yu-Hao Ho

Tsung-Hsiung Lee

Ching-Yi Hsu

Cheng-Tsung Wu

Gene Sheu

Ya-Han Liang

Teng-Shao Su

Chung-Te Chou

Yen-Ni Lee

Rahul Kumar

Shao-Ming Yang

A semiconductor device includes a compound semiconductor layer disposed over a substrate, a protection layer disposed over the compound semiconductor layer, and a source electrode, a drain electrode and a gate electrode which penetrate through the protection layer and are disposed on the compound semiconductor layer. The semiconductor device also includes a gate field plate connecting the gate electrode and disposed over a portion of the protection layer between the gate electrode and the drain electrode. The gate field plate has an extension portion extending into the protection layer.

Semiconductor devices having a gate field plate including an extension portion and methods for fabricating the semiconductor device

A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

Semiconductor device including zener diode and method of manufacturing thereof

A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, and an aluminum gallium nitride layer disposed on the first gallium nitride layer. The semiconductor device also includes an upper recess and a lower recess disposed in the aluminum gallium nitride layer, wherein the upper recess adjoins the lower recess, and the upper recess has a width that is greater than that of the lower recess. The semiconductor device further includes a second gallium nitride layer disposed in the first recess and the second recess, and a gate structure disposed on the second gallium nitride layer. In addition, the semiconductor device includes a source electrode and a drain electrode disposed on the aluminum gallium nitride layer.

Semiconductor devices and methods for manufacturing the same

A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate, a floating gate dielectric on the semiconductor substrate, and a floating gate. The floating gate includes a conductive layer on the floating gate dielectric, and a pair of conductive spacers on a top surface of the conductive layer. The split-gate flash memory cell also includes an inter-gate dielectric covering the floating gate, including sidewalls of the conductive layer and the conductive spacers. The split-gate flash memory cell also includes a control gate on the inter-gate dielectric.

Split-gate flash memory cell and method for forming the same

A method for manufacturing a flash memory includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein the first conductive layer is exposed by an opening of the patterned mask layer. The method also includes forming a second conductive layer on the patterned mask layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening, and performing an oxidation process to form an oxide structure in the opening. In addition, the method includes performing a second etching process by using the oxide structure as a mask to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

Flash memories and methods for manufacturing the same

A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.

Semiconductor structure having a high voltage well region

A split-gate flash memory cell is provided. The split-gate flash memory cell includes a semiconductor substrate having a source region and a drain region. The source region and the drain region are separated by a channel region. The split-gate flash memory cell also includes a concave trench in the semiconductor substrate, a floating gate dielectric lining the concave trench, and a floating gate situated in the concave trench on the floating gate dielectric. The floating gate has a convex bottom surface. The split-gate flash memory cell also includes an inter-gate dielectric on the floating gate, and a control gate on the inter-gate dielectric.

Split-gate flash memory cell having a floating gate situated in a concave trench in a semiconductor substrate

A method for manufacturing a semiconductor device includes forming a first well region in a semiconductor substrate, forming isolation structures on the semiconductor substrate, and forming second well regions and a third well region in the first well region, wherein the second well regions are isolated from the third well region by the isolation structures, and two of the adjacent second well regions have a first distance between them. The method also includes performing a rapid thermal annealing process to shorten the first distance to a second distance. The method further includes forming first barrier metal layers on the first well region and covering the second well regions, forming a second barrier metal layer on the first well region and covering the third well region, forming first electrodes on the first barrier metal layers, and forming a second electrode on the second barrier metal layer.

Schottky diode with dielectrically isolated diffusions, and method of manufacturing the same

A semiconductor device includes a semiconductor substrate having a first conductivity type, and a first well region disposed in the semiconductor substrate, wherein the first well region has a second conductivity type opposite to the first conductivity type. The semiconductor device also includes a buried layer disposed in the semiconductor substrate and under the first well region, wherein the buried layer has the first conductivity type and is in contact with the first well region. The semiconductor device further includes a source electrode, a drain electrode and a gate structure disposed on the semiconductor substrate, wherein the gate structure is located between the source electrode and the drain electrode.

Semiconductor devices and methods for forming the same

A semiconductor structure includes a first high-voltage MOS device region having a first light doping region in a substrate. The conductive type of the substrate is similar to that of the first light doping region. A first well is in the substrate. The first well substantially contacts a side of the first light doping region and does not extend under the first light doping region. The conductive type of the first well is opposite that of the first light doping region. A first gate stack is disposed on a part of the first light doping region and a first well. A first heavy doping region is disposed in the first well and the first light doping region at two sides of the first gate stack. The conductive type of the first heavy doping region is opposite that of the first light doping region.

Semiconductor structure with high-voltage and low-voltage CMOS devices and method for manufacturing the same

A semiconductor substrate structure includes a substrate having a first conductivity type, an oxide layer disposed on the substrate, and a semiconductor layer disposed on the oxide layer. The semiconductor substrate structure also includes a first buried layer disposed in the semiconductor layer, having a second conductivity type opposite to the first conductivity type. The semiconductor substrate structure further includes a second buried layer disposed in the semiconductor layer and above the first buried layer, having the first conductivity type, wherein the first buried layer and the second buried layer are separated by a distance.

Semiconductor substrate structures, semiconductor devices and methods for forming the same

A semiconductor device includes a semiconductor substrate, a first well region, and a second well region. The semiconductor substrate has a first conductivity type. The first and second well regions are disposed in the semiconductor substrate. The first and second well regions have a second conductivity type that is opposite to the first conductivity type. The semiconductor device also includes a first top layer and a second top layer. The first top layer is disposed in the semiconductor substrate. The first top layer extends from the first well region to the second well region. The first top layer has the first conductivity type. The second top layer is disposed in the semiconductor substrate and on the first top layer. The second top layer extends from the first well region to the second well region. The second top layer has the second conductivity type.

Junction field effect transistor (JFET) with first and second top layer of opposite conductivity type for high driving current and low pinch-off voltage

A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer disposed over the substrate; a gate electrode disposed over the epitaxial layer; a source region and a drain region disposed in the epitaxial layer at opposite sides of the gate electrode; a trench extending from a top surface of the epitaxial layer through the source region into the epitaxial layer, wherein the trench has a slanted side and a bottom surface; and a first conductive-type linking region having the first conductive type, wherein the first conductive-type linking region surrounds the slanted side of the trench and contacts the bottom surface of the trench, wherein the first conductive-type linking region electrically connects the source region and the substrate. The present disclosure also provides a method for manufacturing this semiconductor device.

Semiconductor device with a trench and method for manufacturing the same

A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereon; a first well region disposed in a portion of the semiconductor layer; a second well region disposed in another portion of the semiconductor layer; a pair of third well regions disposed in a portion of the semiconductor layer at opposite sides of the second well region; a plurality of isolation elements disposed over the semiconductor layer, respectively between the third well regions and the first and second well region; a deep well region disposed in a portion of the semiconductor substrate adjacent to the semiconductor layer between the first and second well region; a first doping region disposed in the first well region; and second doping regions disposed in the third well regions.

Semiconductor device and method for fabricating the same

The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.

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Dhanbad, India

Manoj Kumar