Tata Consultancy Services Limited

Tata Consultancy Services Lmited

Manoj Karunakara Nambiar

Mahesh Damodar Barve

Sunil Anant Puranik

Swapnil Shashikant Rodi

Dhaval Shah

Ishtiyaque Shaikh

Piyush Manavar

Gautam Shroff

Shruti Kunde

Rekha Singhal

Dheeraj Chahal

Amit Kalele

Mayank Mishra

Nupur Sumeet

Barnali Basak

Sharyu Vijay Mukhekar

Various embodiments disclosed herein provides method and system for low latency FPGA based system for inference such as recommendation models. Conventional models for inference have high latency and low throughput in decision making models/processes. The disclosed method and system exploits parallelism in processing of XGB models and hence enables minimum possible latency and maximum possible throughput. Additionally, the disclosed system uses a trained model that is (re)trained using only those features which the model had used during training, remaining features are discarded during retraining of the model. The use of such selected set of features thus leads to reduction in the size of digital circuit significantly for the hardware implementation, thereby greatly enhancing the system performance.

FPGA implementation of low latency architecture of XGBoost for inference and method therefor

A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware.

Low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware

High level synthesis (HLS) begins with high-level specification of a problem, where behavior is generally decoupled from e.g., clock-level timing. Programming code can be run and debugged during functional simulation using debugging techniques. However, it is not possible to understand execution flow of register transfer level instructions (RTL) generated during RTL debug. Conventionally, it is challenging and not possible due to nature of debugging techniques which ignore printf statements in code for invocation. Systems and methods of present disclosure synthesize printf and/or scanf statements for generating debug messages in HLS code, wherein printf and/or scanf statements is/are included before/after function(s) in sections comprising instructions in code and synthesized as a block during run-time which communicate with host system and debug messages are generated for display on screen. This enables traceability of the code execution on the screen and printf/scanf statements output can be observed without any challenges.

Synthesizing printf and scanf statements for generating debug messages in high-level synthesis (HLS) code

This disclosure generally relates to high-level synthesis (HLS) platforms, and, more particularly, enable print functionality in high-level synthesis (HLS) platforms. The recent availability FPGA-HLS is a great success due to availability of compilers for FPGAs as opposed to hardware description languages (HDLs) that requires special skills. However, the compilers within the HLS design platform includes limited support for all the standard libraries, wherein features like print functionality is not supported. The invention discloses techniques to enable print functionality in HLS design platforms based on source-to-source transformations and stream combining scheme. In addition to enabling print functionality, the invention also discloses a formatter technique to receive-format FPGA data into human interpretable data.

Method and system to enable print functionality in high-level synthesis (HLS) design platforms

A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.

Re-assembly middleware in FPGA for processing TCP segments into application layer messages

This disclosure relates generally to method and system for tuning graphics processing unit (GPU) parameters of a GPU kernel. The disclosure proposes a combination of both heuristic and deterministic techniques for tuning GPU parameters of a GPU kernel to achieve optimal configuration of the GPU parameters. The proposed method and a system for tuning GPU parameters is based on deterministic techniques and heuristic techniques that includes capturing behavior of the GPU application by monitoring several GPU hardware counters that comprise several hardware resources and performance counters. The proposed tuning GPU parameters also implements a set of heuristic techniques to decide course of the tuning for various GPU parameters based on the captured behaviour of the GPU hardware counters.

Method and system for tuning graphics processing unit (GPU) parameters of a GPU kernel

This disclosure relates generally to accelerating development and deployment of enterprise applications where the applications involve both data driven and task driven components in data driven enterprise information technology (IT) systems. The disclosed system is capable of determining components of the application that may be task-driven and/or those components which may be data-driven using inputs such as business use case, data sources and requirements specifications. The system is capable of determining the components that may be developed using task-driven and data-drive paradigms and enables migration of components from the task driven paradigm to the data driven paradigm. Also, the system trains a reinforcement learning (RL) model for facilitating migration of the identified components from the task driven paradigm to the data driven paradigm. The system is further capable of integrating the migrated and existing components to accelerate development and deployment an integrated IT application.

Accelerating development and deployment of enterprise applications in data driven enterprise IT systems

Conventionally, for processing multi-legged orders, matching engines were implemented in software and were connected through Ethernet which is very slow in terms of throughput. Such traditional trading systems failed to process orders of tokens on different machines and these were summarily rejected. Present disclosure provides multiple FPGA system being optimized for processing/executing multi-legged orders. The system includes a plurality of FPGAs which are interconnected for communication via a PCIe port of a multi-port PCIe switch. Each FPGA comprise a net processing layer, a matcher, and a look-up table. Each FPGA is configured to process tokens (e.g., securities, etc.). If orders to be processed are for tokens on same FPGA where the order is received, then tokens are processed locally. Else net processing layer of a specific FPGA routes to specific order request to another FPGA where the tokens (securities) are located thereby reducing the latency and improving overall throughput.

Multiple field programmable gate array (FPGA) based multi-legged order transaction processing system and method thereof

Data processing and storage is an important part of a number of applications. Conventional data processing and storage systems utilize either a full array structure or a full linked list structure for storing data wherein the array consumes large amount of memory and linked list provides slow processing. Thus, conventional systems and methods are not capable of providing simultaneous optimization of memory consumption and time efficiency. The present disclosure provides an efficient way of storing data by creating an integrated array and linked list based structure. The data is stored in the integrated array and linked list based structure by using a delta based mechanism. The delta based mechanism helps in determining the location in the integrated array and linked list based structure where the data should be stored. The present disclosure incorporates the advantages of both array and linked list structure resulting in reduced memory consumption and latency.

Systems and methods for storing data in an integrated array and linked list based structure

The disclosure herein describes a method and a system for message based communication and failure recovery for FPGA middleware framework. A combination of FPGA and middleware framework provides a high throughput, low latency messaging and can reduce development time as most of the components can be re-used. Further the message based communication architecture built on a FPGA framework performs middleware activities that would enable reliable communication using TCP/UDP between different platforms regardless of their deployment. The proposed FPGA middleware framework provides for reliable communication of UDP based on TCP as well as failure recovery with minimum latency during a failover of an active FPGA framework during its operation, by using a passive FPGA in real-time and dynamic synchronization with the active FPGA.

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Thane West, India

Manoj Karunakara Nambiar