Intel Corporation

Manoj I Thadani

Premanand Sakarda

Priya N Vaidya

Bryan C Morgan

Yi Ge

Swee-chin Pang

Zhou Gao

Canhui Yuan

A processing system may include a performance monitoring unit (PMU), a machine accessible medium, and a processor responsive to the PMU and the machine accessible medium. Instructions encoded in the machine accessible medium, when executed by the processor, may determine whether performance details for the processing system should be collected, based at least in part on a predetermined monitoring policy for the processing system. The instructions may generate performance data for the processing system, based at least in part on data obtained from the PMU. The instructions may determine whether the processing system should be reconfigured, based at least in part on the performance data and a power policy profile for the processing system. The instructions may automatically adjust power consumption of the processing system by using the PMU to reconfigure the processing system. Other embodiments are described and claimed.

System and method for adaptive power management based on processor utilization and cache misses

An apparatus and a system, as well as a method and article, may operate to map, by an operating system, a range of virtual addresses to a range of physical addresses, wherein a subset of the range of virtual addresses is identity-mapped to a subset of the range of physical addresses. This range of addresses can then be used by heavy data transfer applications in conjunction with a DMA engine to transfer data between memories, or between memory and input/output devices.

Memory mapping apparatus, systems, and methods

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Marlborough, MA, United States of America

Manoj I Thadani