Apple Inc.

Sun Microsystems, Inc.

Manoj Gopalan

Yu-Yen Mo

Venkat R Podduturi

Shingo Suzuki

Antonietta Oliva

Rajat Goel

Harsha Krishnamurthy

Karthik Rajagopal

Yet-Ping Pai

Dae Suk Jung

Edvin Catovic

Sambasivan Narayan

Seong Rai Cho

Mini Nanua

Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

Context-aware reliability checks

In an embodiment, an integrated circuit may include one or more power gated blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power gated block and a block enable clock. The power gated block may generate local block enables to various power switch segments in the power gated block. In particular, the power gated block may include a set of series-connected flops that receive the block enable from the power manager circuit. The power gated block may include a set of multiplexors (muxes) that provide the local block enables for each power switch segment. One input of the muxes is coupled to the block enable, and the other input is coupled to another enable propagated through one of the other power switch segments. Accordingly, the muxes may be controlled to select the propagated enables or the input block enable.

Power switch ramp rate control using selectable daisy-chained connection of enable to power switches or daisy-chained flops providing enables

A method for inserting flip-flops in an interconnect is provided such that a cycle time constraint for the interconnect is satisfied. First of all, a flop is inserted at an initial placement at a node along a signal path of the interconnect such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net. Secondly, the initial placement of the flop is optimized such that a delay difference, defined by a downstream delay minus an upstream delay, relative to an optimal placement at a downstream node along the signal path of the net is not greater than zero. The disclosed method can also satisfy the flop stage requirement and/or a minimum number of flops requirement for an interconnect.

Flip-flop insertion method for global interconnect pipelining

A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Hierarchical repeater insertion

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Milpitas, CA, United States of America

Manoj Gopalan