Altera Corporation

Cypress Semiconductor Corporation

Manoj B Roge

Joseph Huang

Yan Chong

Michael H M Chu

Philip Clarke

Andrew J Bellis

Chiakang Sung

Rajesh Manapat

Bo Jin

Gary Austin Gibbs

Ajay Srikrishna

Kannan Srinivasagam

Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

Read-leveling implementations for DDR3 applications on an FPGA

Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

PVT compensated auto-calibration scheme for DDR3

I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into single data rate signals, and resynchronizing the single data rate signals. Multiple devices may be accessible with each device potentially having a different clock signal for resynchronizing. Another clock signal may be used to align/synchronize resulting signals from multiple devices. The resynchronized single rate signals can be converted into half-rate data signals, and the four half-rate data signals can be provided to resources in the programmable device core. The input circuit also may provide a half-rate clock signal synchronized with the half-rate data signals to the programmable device core. The half rate clock signal can be derived from the full-rate clock signal using a data strobe signal, a full-rate clock signal, or a half-rate clock signal as an input.

I/O block for high performance memory interfaces

A memory device can provide burst access to row boundary crossing addresses without introducing inter-burst latency. Address locations for a first row of the burst can be accessed at speed, while a prefetch latch can be accessed in lieu of a next row.

Memory device and method for fast cross row data access

Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configuration register and various control signals to determine whether a data transfer operation should be asynchronous or synchronous. The async/sync logic also utilizes the configuration register and various control signals to determine other functionalities of the particular data transfer mode. Functionalities may include normal and page mode, page length, bust read, linear or interleaved burst, burst wrap, burst suspend, data hold length, first access latency, transition between synchronous and asynchronous mode, and the like.

Memory device providing asynchronous and synchronous data transfer

Architecture, circuitry and method are provided for a ternary content addressable memory (TCAM), and use thereof. Each TCAM cell is relatively small in size. If the TCAM cell is called upon to store voltage values indefinitely, provided power is retained on the cell, the TCAM cell employs no more than 16 transistors. Additional savings in size is achieved by using a single common conductor (or dual common conductors in a differential arrangement) to suffice as both the bit line and compare line. The common bit line and compare line connects to not only the X memory cell, but also the Y memory cell and the compare circuit of the TCAM cell. The compare circuit can either be activated or deactivated. During a compare operation, the compare circuit is selectively activated by placing a ground supply upon a match line enable conductor. The ground supply is imputed upon the match line whenever a mismatch occurs to designate that mismatch. Otherwise, during a normal read or write operation, the match line enable is placed at the same voltage value as the pre-charged match line.

Bit encoded ternary content addressable memory cell

Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-&frac12; microns, assuming a 0.15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation. Each CAM cell uses no more than eight conductors per cell, wherein the conductors are of minimum width and pitch arranged co-planar on a single metal layer. Another metal layer utilizes local interconnects and a pair of conductors which carry the differential bit lines and compare lines. The local interconnects do not extend across the entire cell and, therefore, are localized to only a small region of a cell to effectuate power and ground supplies to the CAM cell.

Content addressable memory cell

An apparatus comprising a first circuit, a second circuit, and an output circuit. The first circuit may be configured to generate a first digital output in response to (i) a reference input and (ii) a feedback input. The second circuit may be configured to generate a second digital output in response to (i) the first digital output and (ii) a second feedback input. The output circuit may be configured to generate a third output in response to a data input, wherein an output impedance of the output circuit is adjusted in response to (i) the first digital output and (ii) the second digital output.

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San Jose, CA, United States of America

Manoj B Roge