Google Inc.

Hewlett-Packard Development Company, L.p.

Manohar Karkal Prabhu

Yi Zhang

Bahman Rabii

Gaofeng Zhao

Niyati Yagnik

Michael Eugene Aiello

Timothy S Lipus

Creighton Thomas

Ajay Kumar Bangla

Shilpa Arora

Yingwei Cui

Colin Craig McCulloch

Colin McCulloch

Matthew Strecker Burriesci

Zheng Zhang

Thomas Shimko

Matthew Steven Frisbie

Joshua Nedelka

Keith Wright

Sean Patrick Miller

Johan Kartiwa

Issac VanDuyn

Yingweii Cui

A method and system for adjusting ads auction using predicted user responses to an in-ad survey is provided. The method includes (1) providing a content item associated with an actionable object, which when selected, causes a computing device to present a plurality of interactive elements each corresponding to a different one of a plurality of reasons for restricting the content item; (2) receiving, from the computing device, data indicating a particular reason, of the plurality of reasons, for restricting the content item, and the particular reason corresponding to a particular interactive element, of the plurality of interactive elements, that was selected by the user; and (3) updating, using the received data, a content selection model for selecting content items, wherein the content selection model is associated with the user.

Adjust ads auction using predicted user response to an in-ad survey

The present disclosure selects third party content based on feedback. A selector identifies several content items including first and second content items (or more) responsive to a request. A machine learning engine determines a first feature of the first content item, a second feature of the second content item, and a third feature of the web page or a device associated with the request. The machine learning engine determines, responsive to the first feature and the third feature, a first score for the first content item based on a machine learning model generated using historical signals received from devices via a metadata channel formed from an electronic feedback interface. The machine learning engine determines a second score for the second content item responsive to the second feature and the third feature. A bidding module determines a price for the first content item based on the first and second scores.

Systems and methods for selecting third party content based on feedback

Display screen with transitional graphical user interface

A preemptive write back controller is described. The present invention is well suited for a cache, main memory, or other temporarily private data storage that implements a write back strategy. The preemptive write back controller includes a list of the lines, pages, words, memory locations, or sets of memory locations potentially requiring a write back (i.e., those which previously experienced a write operation into them) in a write back cache, write back main memory, or other write back temporarily private data storage. Thus, the preemptive write back controller can initiate or force a preemptive cleaning of these lines, pages, words, memory locations, or sets of memory locations.

Preemptive write back controller

A checkpointing method and system that utilize a write back controller. The system can include a first controller for implementing a first function, wherein the first function comprises part of a checkpoint operation and wherein the checkpoint operation comprises a series of contiguous checkpoint cycles. The system can also include a second controller, the second controller for implementing a second function, wherein the second function comprises a write back operation from a first memory location to a second memory location and wherein the write back operation occurs before a checkpoint cycle ends. Information already at the second memory location can be selectively written back to a third memory location.

Checkpointing with a write back controller

The present invention, in various embodiments, provides techniques for testing devices. In one embodiment, the device under test is a chip including a plurality of processors and a memory structure that stores test programs. One or more processors executes the test programs and generates test results based on which the chip may be determined good or bad. In one embodiment, the processors execute the test programs independent of each other, and no external hardware and/or test controller is required during the test phase. Various embodiments include a first processor that controls the scan chain of a second processor; the test results of the first processor are used as inputs for testing the second processor, etc.

Testing processors

A method for conducting checkpointing within a writeback cache having a cache memory with at least two memory banks. In one embodiment, a first pointer is set to indicate which cache entry of the at least two memory banks contains current data. A second pointer is set to indicate which cache entry of the at least two memory banks contains checkpoint data. Checkpointing is performed by selectively controlling said second pointer or said first pointer.

Method for conducting checkpointing within a writeback cache

A fault-tolerant computer system having an application memory organized as a plurality of cache lines, each cache line being identified by an address in the memory. A FIFO buffer stores a plurality of such cache lines. The system includes at least one CPU for executing instructions stored in the application memory. A checkpoint controller defines a series of repeating checkpoint cycles. The application memory and FIFO buffer are operated under the control of a memory controller. The checkpoint controller also has access to a plurality of registers in the CPU that define the state of that CPU at a point in each checkpoint cycle that is controllable by the controller. When the memory controller receives a cache line from the CPU in response to a write command specifying an address A in the application memory at which the cache line is to be stored, a copy of the cache line as stored in the application memory at A is copied into the FIFO buffer upon receiving the first write command specifying A after the start of the current checkpoint cycle. The cache line received in the write command is then used to overwrite the contents of address A in the application memory. At a predetermined point in each checkpoint cycle, the checkpoint controller causes the CPU to write back to the memory all dirty cache lines; and to store its internal registers defining the state of the CPU in the state memory. The checkpoint controller empties the contents of the FIFO buffer at the end of each checkpoint cycle if no error has been detected by the end of the checkpoint phase of the cycle. If an error is detected, the contents of the FIFO buffer are read back into the application memory, and the contents of the state memory are read back into the CPU. The system is then restarted after completing any hardware configuration needed for the restart.

Checkpoint computer system utilizing a FIFO buffer to re-synchronize and recover the system on the detection of an error

Growing community of inventors

Pal Alto, CA, United States of America

Manohar Karkal Prabhu