Micron Technology Incorporated

Manny K Ma

James E Miller, Jr

Gordon D Roberts

Daryl L Habersetzer

Jeffrey D Bruce

Eric T Stubbs

Kurt D Beigel

Stephen L Casper

Joseph C Sher

Douglas John Cutter

Wen Qian Li

Troy A Manning

Kevin G Duesman

Aaron M Schoenfeld

Stephen R Porter

Brian M Shirley

Trung Tri Doan

Alan R Reinberg

Zhiqiang (Jeff) Wu

Jeff Zhiqiang Wu

Jeffrey P Wright

R Jacob Baker

Chris G Martin

Yauh-Ching Liu

Rajesh Somasekharan

Glen Earl Hush

David A Cathey

Mirmajid Seyyedy

David A Zimlich

Michael D Chaine

Craig M Dunham

Kurt D Biegel

As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

Method of preparing to test a capacitor

An electrostatic discharge protection device is formed in a substrate and contains a drain area of a first dopant concentration abutting an extended drain area having a dopant concentration lower than the first dopant concentration. Similarly, a highly doped source area abuts a lower doped source extension area. The source and drain are laterally bounded by oxide regions and covered by an insulation layer. The areas of lower doping prevent charge crowding during an electrostatic discharge event by resistively forcing current though the nearly planer bottom surface of the drain, rather than the curved drain extension. In addition, a highly doped buried layer can abut an area of a graded doping level. By adjusting the doping levels of the graded areas and the buried layers, the substrate breakdown voltage is pre-selected.

Electrostatic discharge protection device having a graded junction and method for forming the same

Circuit and method for voltage regulation in a semiconductor device

An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.

Advance metallization process

An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.

CMOS output driver for semiconductor device and related method for improving latch-up immunity in a CMOS output driver

Method of compensating for a defect within a semiconductor device

A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.

Semiconductor device having increased breakdown voltage and method of fabricating same

Method for forming a field effect transistor having increased breakdown voltage

Driver circuit for a voltage-pulling device

Method of fabricating a semiconductor device having increased breakdown voltage

Method of stressing a memory device

The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers. According to another aspect, a masking material layer comprises a bi-level profile having two different layer elevational thicknesses, the greater of which being disposed immediately laterally adjacent a contact opening pattern. A contact opening is etched through the substrate outer surface and conductive material is formed therein to electrically connect the substrate location with an outer conductive layer. In a preferred implementation, the masking material layer or photoresist is formed through photolithography using only a single mask. In another implementation, more than one mask is used to define the multi-level or bi-level profile masking material layer. The multi-level masking layer can have more than two levels.

Semiconductor processing methods of forming a contact opening

Growing community of inventors

Boise, ID, United States of America

Manny K Ma