Texas Instruments Corporation

Manjunath Rudranna Hadli

Kedar Satish Chitnis

Brian Okchon Chae

Brijesh Rameshbhai Jadav

David Edward Smith, Jr

Sivaraj Rajamonickam

Purushotam Kumar

Brijesh Rameshbhal Jadav

A video processor controlled by a set of non-shadow registers is provided. A list of updates for one or more of the non-shadow registers may be prepared in a memory module. A frame buffer is updated with video data for a display coupled to the video processor. A blanking interval is detected after updating the frame buffer. A direct memory access engine is triggered to transfer the list of updates from the memory module to the non-shadow registers during the blanking interval.

Updating non-shadow registers in video encoder

A method for capturing video frames from a plurality of video channels is provided. A list of a least two descriptors is formed for each of the plurality of video channels in a memory accessible to a direct memory access (DMA) engine, wherein each of the two or more descriptors for each channel is programmed to define a storage location for a sequential frame of video data for the channel. A sequence of video frames is received from the plurality of video channels, wherein for each channel, video frames are received at a frame rate for that channel. A DMA engine uses descriptors from the list to store video frames as they are received. The list is updated periodically to replace used descriptors.

Video capture from multiple sources

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Belguam, India

Manjunath Rudranna Hadli