Iqm Finland Oy

Manjunath Ramachandrappa Venkatesh

Juha Hassel

Mikko Möttönen

Tianyi Li

Kok Wai Chan

Johannes Heinsoo

Wei Liu

Hasnain Ahmad

Kuan Yen Tan

Caspar Ockeloen-Korppi

Máté Jenei

Lily Yang

Jean-Luc Orgiazzi

Alessandro Landra

Mario Palma

Vasilii Sevriuk

The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

Electroplating for vertical interconnections

This disclosure describes a superconducting device comprising a trench and a cavity that extends through a superconducting base layer. The trench crosses the cavity. The superconducting device further comprises a first junction layer that extends from a first region of the superconducting base layer to the cavity, an insulating layer on the surface of the first junction layer, and a second junction layer that extends from a second region of the superconducting base layer to the cavity. The second junction layer overlaps with the insulating layer on the bottom of the cavity. The disclosure also describes a method for producing this disclosed superconducting device.

Superconducting device

The present invention relates to the manufacture of Josephson junctions. Such Josephson junctions may be suitable for use in qubits. High-quality, potentially monocrystalline, electrode and dielectric layers are formed using blanket deposition. Subsequently, the structure of one of more Josephson junctions is formed using multi-photon lithography to create openings in a resist followed by etching the electrode and dielectric layers.

Method for manufacturing Josephson junctions

Growing community of inventors

Espoo, Finland

Manjunath Ramachandrappa Venkatesh