International Business Machines Corporation

Manjul Bhushan

Mark B Ketchen

Edward P Maciejewski

Chandrasekharan Kothandaraman

Chin Kim

Wilfried Haensch

Brian L Ji

Dale J Pearson

Karen M G V Gettings

Qingqing Liang

Chandramouli Visweswariah

Keith Aelwyn Jenkins

Barry P Linder

James Douglas Warnock

Stephen Gerard Shuma

Jae-Joon Kim

Michael H Wood

Debjit Sinha

Aditya Bansal

Kai Zhao

Eric Jason Fluhr

Carl J Anderson

A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M) in the integrated circuit device.

Single level of metal test structure for differential timing and variability measurements of integrated circuits

A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.

Reducing performance degradation in backup semiconductor chips

A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.

A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors.

Active 2-dimensional array structure for parallel testing

An approach for performing device-based random variability modeling in timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design is described. In one embodiment, an algorithm is derived from results of simulating the operational behavior of a representative digital integrated circuit. A timing analysis is performed on the device-level custom design part of the digital integrated circuit to obtain device-level random variability sensitivity values. A gate-level characterization is performed on the gate-level design part of the digital integrated circuit to obtain logic gate random variability sensitivity values. A timing analysis is performed on the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.

Device-based random variability modeling in timing analysis

A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.

High speed measurement of random variation/yield in integrated circuit device testing

A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.

Measurement of partially depleted silicon-on-insulator CMOS circuit leakage current under different steady state switching conditions

A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.

Acquisition of silicon-on-insulator switching history effects statistics

Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.

Methods and apparatus for determining a switching history time constant in an integrated circuit device

An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m&#xd7;n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.

Methods and apparatus for inline variability measurement of integrated circuit components

An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Methods and apparatus for pulse generation used in characterizing electronic fuses

An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal.

M1 testable addressable array for device parameter characterization

Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit

Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

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Hopewell Junction, NY, United States of America

Manjul Bhushan