General Electric Company

Philips Electronics North America Corporation

North American Philips Corporation

Manjin J Kim

Dale M Brown

Bernard Gorowitz

Satyendranath Mukherjee

Richard J Saia

Bruce F Griffing

Tat-Sing P Chow

Simon S Cohen

Bantval J Baliga

Theodore James Letavic

Charles S Korman

Mario Ghezzo

Richard D Baertsch

David William Skelly

Ronald H Wilson

Thomas L Vogelsong

Robert W Stoll

Krishna Shenai

Patricia A Piacente

Arlene G Williams

Jein-Chen Young

A process is set forth for providing a self-aligned, vertical bipolar transistor. A controlled technique is provided for providing the base and emitter features of the transistor with appropriate dimensions and properties to be useful in high frequency microwave applications. A microwave transistor is provided by this technique.

Method of manufacturing a self-aligned vertical bipolar transistor

A microwave monolithic integrated circuit includes a coplanar waveguide (CPW) formed by a composite silicon structure constituted by a relatively high resistivity substrate, a first oxide layer on the upper surface thereof, a relatively thin silicon layer formed on the surface of the first oxide layer, and a very thin second oxide layer formed on the surface of the thin silicon layer. The silicon layer and the first oxide layer on which it is formed constitutes a silicon-on-insulator or SOI structure. A metallic signal line and ground planes are bonded to the surface of the second oxide layer. The zone of the thin silicon layer which extends between the ground planes is doped with an active impurity to produce high conductivity therein. As a result, the electric component of a quasi-TEM wave traversing the waveguide is substantially restricted to the thin silicon layer and does not penetrate to the underlying bulk silicon substrate. This achieves significantly reduced transmission loss and a quality factor Q in the vicinity of 17 for the CPW. Passive and active circuits may be formed in regions of the thin silicon layer other than those used for the CPW.

Microwave monolithic integrated circuit with coplaner waveguide having

A technique for making a microwave, high power SOI-MOFET device is set forth together with such a device. An important aspect of this structure is the presence of high conductivity metal gate fingers for the device.

Microwave power SOI-MOSFET with high conductivity metal gate

A monolithic microwave integrated circuit (MMIC) is produced by a method which forms multilevel conductive members, including thick low-loss metallic members. The low-loss metallic members are particularly useful for forming inductors and interconnecting circuit components. The MMIC is formed on a thick oxide layer of a silicon-on-insulator structure having a high-resistivity silicon substrate to inhibit RF interaction with the substrate.

Monolithic microwave circuit with thick conductors

A method is set forth for forming a plurality of SOI transistors in a pattern beneath planarized reflective surfaces of a reflective display. This enables the formation of information pixels useful in devices, such as reflective LCD devices. A specific technique of providing the SOI transistors is set forth.

Method of manufacturing a reflective display

A vertical double diffused metal-on-semiconductor device is produced by a method involving the formation of horizontally separated bodies of heavily doped Si and sources by a self-aligned process and a lift-off process along with the formation of trenches having negatively-sloped side-walls.

Method of producing VDMOS device of increased power density

A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using edges of the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

Vertical power MOS device with increased ruggedness and method of

A nonvolatile storage device is provided with at least one stacked poly gate structure formed on the substrate and disposed between a first trench and a second trench. The trenches each having two walls. A first doped area having a first conductivity type extending along the wall of the first trench and a second doped area having a second conductivity type extending along the wall of the second trench. The first doped area and the second doped area having heights greater than widths, the heights being parallel to the trench walls and the widths being perpendicular thereto. The trench walls are lined with a metal silicide to decrease resistivity.

Electrically erasable and programmable read-only memory with source and

A semiconductor device of improved ruggedness is provided which comprises a semiconductor substrate having a region of a first conductivity type on a major surface thereof; a first base region of opposite conductivity type formed selectively within said regions of first conductivity type; a second base region of opposite conductivity type formed selectively within said first base region and having a higher impurity concentration than that of said first base region; a source region of one conductivity type formed within said first and second base regions and overlying said second base region; and a polysilicon gate electrode opposed to a channel region with a gate insulating layer interposed therebetween; wherein the second base region and the source region are formed substantially entirely within the first base region; the second base region is smaller in depth than the first base region and is formed at a distance sufficiently close to the channel region to effectively reduce parasitic resistance in the first base region, the lateral edges of the second base region being substantially aligned with the lateral edges of the gate electrode; the first base region and the source region are formed by sequential implantation through the polysilicon gate electrode region using the polysilicon gate electrode as a self-aligned mask, followed by implantation of the second base region without substantial lateral diffusion using the polysilicon gate electrode as a mask; and the polysilicon gate electrode is of a thickness sufficient to mask for selected depths of implantation in the first base region.

A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this high conductivity layer allows a substantially smaller contact window to be employed for making contact between the final metallization and the source region. As a consequence, the aperture in the gate electrode and the cell size of the device can both be substantially reduced. The device has substantially improved operating characteristics. A method of producing the device is also described.

Power field effect devices having small cell size and low contact

A metal for fabricating contact structures through via openings in VLSI circuits employs a dual layer of refractory metal. A thin titanium layer is deposited, over which a molybdenum layer is formed. An annealing treatment further improves contact resistance characteristics. The method results in a contact structure which exhibits desirable properties of thermal compatibility, step coverage, contact resistance and improved processing characteristics.

MO/TI Contact to silicon

A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon of low resistivity to form a low resistance contact therewith.

Ohmic contacts and interconnects to silicon and method of making same

Molybdenum gate electrode material is provided with an upper layer of molybdenum nitride which acts to prevent deposition of source and drain contact metal by selective chemical vapor deposition (CVD). The nitride layer also provides an improved mask for ion implantation process steps. This results in an FET structure exhibiting a high degree of planarity which is desirable for multilevel device fabrication.

Active area planarization with self-aligned contacts

A conductive member consisting of a first conductor of an alloy of titanium and tungsten and a second conductor of a refractory metal such as molybdenum is sintered to a conductive member of silicon to a temperature in the range of 600.degree. C. to 650.degree. C. in a reducing atmosphere to form a low resistance contact.

Method of making mo/tiw or w/tiw ohmic contacts to silicon

A layer of aluminum oxide or other insulative metal oxide is employed as an etch stop in the fabrication of very large scale integrated circuit devices. The use of such etch stops permits fabrication of unframed or borderless via openings and correspondingly permits greater metallization line pitch, smaller circuit features, and more reliable interlayer electrical contact. A method for insulative metal oxide deposition is also described.

Growing community of inventors

Schenectady, NY, United States of America

Manjin J Kim