Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Manish Umedlal Patel

Vikash

Setti Shanmukheswara Rao

Dharmendra Kumar Rai

Manish Trivedi

Mohammed Rahim Chand Seikh

Diwakar Ramadasu

Shailendra Sharad

A circuit generates low-skew true and complement output signals from an input signal using an inverter, true signal generation circuitry, and complement signal generation circuitry. The inverter operates between a high-voltage reference source (VDD) and a low-voltage reference source (VSS) and inverts the input signal to generate a delayed complement input signal. The true signal generation circuitry, which comprises a p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a true output signal. The complement signal generation circuitry, which also comprises p-type transistor in series with an n-type transistor, (i) operates between (a) one of VDD and VSS and (b) one of the true input signal and the complement input signal and (ii) generates a complement output signal.

Concurrent true and complement signal generation

A memory cell array includes local input/output logic configured to access memory cells in memory banks. The memory cell array includes inner memory banks disposed in either direction from the local input/output logic. The memory cell array includes outer memory banks disposed beyond the inner memory banks in either direction from the local input/output logic. The memory cell array further includes local bitlines that run in a lower metallization layer of each of the memory banks. The local bitlines of the outer memory banks connect to the local input/output logic via an upper metallization layer across regions of the inner memory banks.

Memory banks with shared input/output circuitry

A memory device includes a memory array comprising a including of memory cells, and control circuitry coupled to the memory array. The control circuitry includes write signal generation circuitry configured to provide a write clock signal for controlling writing of data to portions of the memory array, with timing of the write clock signal being determined at least in part utilizing a parallel combination of two or more additional memory cells external to the memory array. The parallel combination of additional memory cells may comprise a mini-array that includes centrally-located active memory cells surrounded by dummy memory cells. In an arrangement in which the write signal generation circuitry includes a clock latch, the parallel combination of additional memory cells may be coupled between a clock output of the clock latch and a reset input of the clock latch.

Memory device having control circuitry configured for clock-based write self-time tracking

A static memory system with multiple memory cell that, in response to a reset signal, simultaneously resets or clears a segment of the memory cells in the memory. Clearing the entire memory or a portion thereof is accomplished by sequencing though a subset of address bits while asserting the reset signal.

Static memory with segmented clear

A memory device includes a memory array including a plurality of memory cells, sensing circuitry coupled to at least a given bitline associated with a particular column of the memory cells of the memory array, and access time acceleration circuitry coupled to the bitline. The access time acceleration circuitry is configured to control an amount of time required by the sensing circuitry to access data stored in a given one of the memory cells in the particular column of memory cells, by providing in a current access cycle at least a selected one of a plurality of different supplemental charging and discharging paths for the bitline based at least in part on data accessed using the bitline in a previous access cycle. By way of example, the different supplemental charging and discharging paths may comprise an additional pull-up path configured to supplement operation of a pull-up path of the given memory cell and an additional pull-down path configured to supplement operation of a pull-down path of the given memory cell.

Growing community of inventors

Bengaluru, India

Manish Umedlal Patel