Qualcomm Incorporated

Synopsys, Inc.

Hewlett-packard Development Company, L.p.

Manish Srivastava

Venugopal Boynapalli

Qi Ye

Venkat Narayanan

Basannagouda Somanath Reddy

Pradip Subhana Jadhav

Neha Gupta

Ajit Malaviya

Samarth Vasishtha

Esakkimuthu Dhakshinamoorthy

Satadru Sarkar

A True Single Phase Clock (TSPC) latch design with symmetrical input data paths. A first input data path includes: a first NMOS transistor coupling a gate of a first PMOS transistor to VSS in response to a rising input data signal, and a second PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the first and second PMOS transistors turn on to couple a data input node to VDD. A second input data path includes: a third PMOS transistor having a gate coupled to a falling input data signal (VSS), a fourth PMOS transistor having a gate coupled to a logic low (VSS) input clock signal, whereby the third and fourth PMOS transistors turn on to couple a gate of a second NMOS transistor to VDD, whereby the second NMOS transistor turns on to couple the data input node to VSS.

High performance and low power TSPC latch with data agnostic setup and hold time

A full adder is provided in which a sum logic circuit for producing the sum signal and a carry-out logic circuit for producing the carry-out output paths do not share internal nodes. In addition, the sum logic circuit and the carry-out logic circuit are both configured to obviate the need for transmission gates with respect to forming the sum signal and the carry-out signal.

Performance power optimized full adder

Aspects of the disclosure are directed to a voltage level shifter architecture, including a voltage level shifter with circuitry residing within a footprint; and an internal augmented voltage generator residing within the footprint, wherein the internal augmented voltage generator is coupled to the voltage level shifter to augment a voltage level shift.

Augmented intermediate voltage generator based core to pad level shifter

A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.

High-speed soft-edge sense-amplifier-based flip-flop

A multi-bit flip-flop (MBFF) includes a plurality of 1-bit flip-flops, each having an input data selection circuit that receives a data signal and a scan data signal. The MBFF also includes a local signal generation circuit that receives a global clock signal and a global scan enable signal, and in response, provides local control signals, wherein each of the local control signals is generated in response to both the global clock signal and the global scan enable signal. The local control signals are provided to the input data selection circuits, and exclusively control the input data selection circuits to route either the input data signal or the scan input data signal as a master data bit, reducing transistor requirements. Local clock signals may be generated by the local signal generation circuit in response to the global clock signal, and may exclusively control data transfer within the flip-flops, improving setup time.

Area-delay-power efficient multibit flip-flop

Methods and apparatus are disclosed in which locks for shared data are acquired by specifying a pathname for the shared data. One embodiment, among others, includes a method for locking shared data. The method includes the steps of receiving a first request to acquire a lock for a first pathname, storing the first pathname in a lock store, searching the lock store for a corresponding pathname in response to a further request to acquire a lock for a second pathname, and if the second pathname corresponds to the first pathname in the lock store then denying the further request to acquire the lock for the second pathname.

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Bengaluru, India

Manish Srivastava