Sun Microsystems, Inc.

Cadence Design Systems, Inc.

Manish Singh

Bruce W McGaughy

Arun Chandra

Prashant Karhade

Bhaskar Subramanian

Peng Wan

The method and apparatus for analysis of integrated circuits using static timing analysis. For a circuit being analyzed, the value of the state net for the case of an undriven sensitization is resolved to a Hi/Lo logic on the output net and the sensitization is added to the appropriate pull-up/pull-down function on the output net. Furthermore, in the sensitization generation, the 'present' state logic function at the output net is determined by the 'previous' state variable of the sequential state net and the &#x201c;present&#x201d; state variables of the rest of the inputs to the sequential circuit. The &#x201c;next&#x201d; state logic function at the output net is determined by the &#x201c;present&#x201d; state variable of the sequential state net and the &#x201c;next&#x201d; state variables of the rest of the inputs to the sequential circuit. This variable is resolved as a function of &#x201c;previous&#x201d; state net variable and &#x201c;present&#x201d; state input net variables. In the present invention, a BDD XOR operation of the &#x201c;present&#x201d; state function and the &#x201c;next&#x201d; state function at the output net is used to determine the set of possible transitions at the output in terms of the transitions at the inputs. This function is further constrained with single input switching constraint. The resultant BDD describes the output net transition in terms of single input switching for every input to the sequential circuit.

Automatic device strength based sensitization generation for sequential elements

A machine-implemented, simulations-supporting system creates a hierarchy of data structures for simplifying the task of identifying iso-topological, and iso-geometric, and iso-static instances of subcircuit-definitions. The behaviors of such isomorphic and iso-static instances can be simultaneously predicted by appointing a simulation leader for them and using the simulation leader in combination with a respective simulation model to predict the behavior of the simulation leader. The predicted behavior of the leader is then copied for the followers. In one embodiment, state-describing S-circuit cards each point to a respective, and possibly merged, I-circuit card. The I-circuit cards each point to respective, and possibly merged, element instantiating cards (AG-cards) as well as to respective, and possibly merged, interconnect-topology describing cards (T-circuits). If the handles (SH's) of two or more subcircuit parts point to a same, state-describing S-part, where the latter points to a merged I-circuit, and where the latter points to a merged T-circuit, then it can be determined by this that the respective subcircuit parts are both isomorphic and substantially iso-static and can therefore follow a commonly appointed leader. The disclosed system can be used with fully-flattened design definitions as well as with highly hierarchical design definitions.

Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure

A method and apparatus for improved formal equivalence checking to verify the operation of components in a VLSI integrated circuit. The present invention enhances previous techniques for dynamic circuits by generating a multi-level transistor abstraction for dynamic circuits. Two-levels of abstracted code are generated. First, an abstracted legal Verilog&#xae; is generated for the evaluate phase of a dynamic circuit. Second, 'comment-logic' in Verilog&#xae; syntax is generated for the pre-charge phase of the dynamic circuit. Using the method and apparatus of the present invention, it is possible to obtain a multi-level transistor abstraction for both the 'clk=0' and the &#x201c;clk=1&#x201d; conditions. The binary decision diagram property of the circuit being analyzed is used to generate multi-level representations for both the pre-charge (clk=0) and the evaluate phases (clk=1). The multi-level abstracted model of the present invention has several advantages over the prior art. The legal Verilog&#xae; can be used for traditional simulation and equivalency verification, ATPG. The &#x201c;comment logic&#x201d; can be used with a property checking tool to verify that the clock connectivity is correct. In addition, the present invention has the advantage of being able to generate legal Verilog&#xae; with pre-charge for verification against RTL with detailed pre-charge information.

Growing community of inventors

Sunnyvale, CA, United States of America

Manish Singh