Synopsys, Inc.

Manish Shroff

Alexander Rabinovitch

Baijayanta Ray

Bojan Mihajlovic

Alex Rabinovitch

Xavier Guerin

Circuit designs are emulated to verify the functionality of the circuit design. Emulating the circuit design includes obtaining a circuit design. The circuit design includes clock signals. Each of the clock signals is a data path clock signal. Further, a first clock signal of the clock signals is determined to be faster than a second clock signal of the clock signals. Rising edges and falling edges of the second clock signal are aligned with rising edges of the first clock signal to generate a realigned clock signal based on determining that the first clock signal is faster than the second clock signal. The circuit design is emulated using the realigned clock signal.

Clock signal realignment for emulation of a circuit design

A system and method for emulation receives a circuit design driven by a primary clock signal. The circuit design includes reset circuitry and sequential circuitry connected to the reset circuitry. The circuit design includes a secondary clock signal that is slower than the primary clock signal. The reset circuitry generates a reset signal that is a function of the secondary clock signal. The secondary clock signal is remodeled at a transition edge of the primary clock signal, and a predicted reset signal is generated subsequent to the reset signal at the transition edge of the primary clock signal. An operation of the circuit design is emulated based on the predicted reset signal such that the predicted reset signal from the reset circuitry propagates through multiple cycles of the primary clock signal.

Multicycle path prediction of reset signals

The independent claims of this patent signify a concise description of embodiments. An emulation control block enables a user to view an entire design in the same phase so that the used can observe and control a halted design in the same logical reference cycle. Both the clock cone and design flops are provided in the state which occurs after the evaluation of cycle K of the reference time. During cycle K+1 of an emulation, the values of derived clocks for cycle K+1 are computed. Moreover, during cycle K+1 of the emulation, the values of the sequential elements are computed based cycle K values of the clocks. When the emulation is halted due to a break, the clock cone is reverted to its previous state. This Abstract is not intended to limit the scope of the claims.

Coherent observability and controllability of overlaid clock and data propagation in emulation and prototyping

Embodiments of a computer system for simulating a circuit are described. During a first mode of the simulation, the computer system stores primary signals and circuit relationships between primary signals and secondary signals associated with a portion of the circuit in a file, where the primary signals are independent of gate outputs in the portion of the circuit, and the secondary signals are driven by gates in the portion of the circuit. Moreover, during a second mode of the simulation, the computer system stores dynamic changes in additional relationships between signals to the file, where the signals can include primary signals, secondary signals, or both.

Growing community of inventors

Marlborough, MA, United States of America

Manish Shroff