Freescale Semiconductor,inc.

Tagore Technology, Inc.

Manish N Shah

Daniel Lee Kaczman

Amitava Das

Lawrence Edwin Connell

Mahibur Rahman

Charles LeRoy Sobchak

Joseph P Golat

Syed Asif Eqbal

Mohammed S Alam

Mohammed Rachedine

Sudhir Gouni

Subhendu Rana

Firdos Khan

Pramit Sarkar

David L Cashen

Procheta Chatterjee

Lu M Han

Rajesh Ghosh

An electronic device includes a GaN power FET, a GaN driver coupled to the GaN power FET and a gate bias circuit coupled to the GaN driver. The GaN power FET and the GaN driver are monolithically integrated on a single GaN die. The gate bias circuit is predominately monolithically integrated on the single GaN die and includes only one active component external to the single GaN die. In one embodiment, the only active component external to the single GaN die is a linear regulator. In another embodiment, the only active component external to the single GaN die is a shunt regulator. In yet another embodiment, the only active component external to the single GaN die is a Zener diode.

Gate bias circuit for a driver monolithically integrated with a GAN power FET

An integrated circuit includes a substrate, a GaN FET power switch disposed on the substrate, and a totally-GaN-based driver disposed on the substrate and coupled to the GaN FET power switch. The totally-GaN-based driver has an input terminal for receiving a supply voltage and includes an under-voltage detector having an output terminal. The under-voltage detector outputs a UVLO signal when the supply voltage is below a low-to-high threshold value, and does not output the UVLO signal when the supply voltage is above the low-to-high threshold value. The totally-GaN-based driver includes a pulse stretcher having an input terminal coupled to the output terminal of the under-voltage detector, and an output terminal for outputting a stretched_UVLO signal for a predetermined amount of time after the supply voltage first rises above the low-to-high threshold value.

Under voltage lock-out circuit

An electronic circuit, integrated circuit, and method for a bias-less Miller clamp protection circuit, electrically coupled to an output of a driver circuit and to an input gate of a semiconductor switch device, for dynamically protecting the semiconductor switch device from turning from an off state to an on state in response to a parasitic Miller turn-on signal at the gate, regardless of the bias-less Miller clamp protection circuit having, or lacking, a power supply that provides electrical power to the bias-less Miller clamp protection circuit. The semiconductor switch device can include one or more GaN switch devices. The bias-less Miller clamp protection circuit does not consume any current during normal operation of the electronic circuit and also does not cause any interference to the normal operation.

Bias-less dynamic miller clamp

A HEMT cell includes two or more gallium nitride ('GaN') high-electron-mobility transistor ('HEMT') devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (&#x201c;2DEG&#x201d;) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.

High performance radio frequency switch

An adjustable threshold power limiter circuit. A number of switching elements are included with at least a first and second switching element that each has a first terminal, a second terminal, and an insulated gate terminal. The switching elements forming a conductive path between its first and second terminals based on a voltage between its insulated gate terminal and one of its first or terminal exceeding a threshold. A conductive path is present with a series connection of the switching elements between a signal input and a reference potential. A controller is included and is electrically coupled to each insulated gate terminal of each switching element to independently provide to each insulated gate terminal either an on voltage or an off voltage.

High speed programmable threshold gallium nitride power limiter

A HEMT cell includes two or more gallium nitride ('GaN') high-electron-mobility transistor ('HEMT') devices electrically connected in series with each other. The HEMT cell includes a HEMT cell drain, a HEMT cell source, and a HEMT cell gate. The HEMT cell drain connects with the drain of a first GaN HEMT device in the series. The HEMT cell source connects with the source of a last GaN HEMT device in the series. The HEMT cell gate connects to a first two-dimensional electron gas (&#x201c;2DEG&#x201d;) gate bias resistor that connects with the gate of the first GaN HEMT device. The HEMT cell gate connects to a second 2DEG gate bias resistor that connects with the gate of the second GaN HEMT device. The first and second 2DEG gate bias resistors are located in a 2DEG layer of the HEMT cell. A multi-throw RF switch is also disclosed.

A balanced mixer circuit (and) in a baseband receiver () includes an oscillator circuit (), a mixer (and), a digital-to-analog converter (and) and a digital signal processor (). The mixer includes CMOS devices (and). In response to differential outputs from the mixer, the digital signal processor controls the digital-to-analog converter to output bias voltages for the gate of at least one of the CMOS devices of the mixer to compensate for imbalance in the differential output of the mixer that may be caused by mismatch among two or more CMOS devices of the mixer or caused by other reasons, in order to increase second order intercept point of the mixer.

Mixer circuits for second order intercept point calibration

Methods and corresponding systems for receiving a radio frequency signal include a receiver capable of switching operating modes and operable to receive the radio frequency signal in any of the operating modes. A metric monitor is coupled to the receiver and operable to provide a metric. A controller is responsive to the metric and operable to switch the receiver between the operating modes. The operating modes can include a zero intermediate frequency (ZIF) mode and a very low intermediate frequency (VLIF) mode. The metric can include a received signal strength indicator (RSSI) and an adjacent channel indicator. The receiver can be configured to operate in the ZIF mode in response to the RSSI value satisfying a threshold and configured to operate in the VLIF mode in response to the RSSI value failing to satisfy the threshold.

Receiver configurable in a plurality of modes

An IPtuning circuit (and) for tuning the IPof a mixer (and) to minimize second order intermodulation distortion (IMD) in a receiver (and) of a transceiver (and). An operating characteristic of the mixer related to IMDis changeable by changing a value of a setting of the mixer. Two tones outside a bandpass of the receiver are injected into the mixer and a calibration tone within the bandpass is produced as a result of IMD. Alternatively, a DSSS signal is injected into the mixer and the calibration tone is produced at a chip rate of the DSSS signal. The power of the calibration tone is measured at a plurality of values of the settings. Alternatively, a four-level PN DSSS signal of known content is injected into the mixer, and a two-level PN DSSS signal of known content produced therefrom is correlated with a two-level PN DSSS signal of known content produced by a squaring circuit ().

Tuning a second order intercept point of a mixer in a receiver

A high performance radio frequency receiver includes an isolated transconductance amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to multiple electrically isolated currents; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. IIP2 calibration of the in-phase and quadrature channels may be optimized using the isolated transconductance amplifier.

Split channel receiver with very low second order intermodulation

A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. Decreased die size, current drain, cost, and complexity, as well as improvements in gain, 1/f noise, noise figure, sensitivity, and linearity may result.

High performance CMOS radio frequency receiver

A method and apparatus are provided for providing improved radio frequency (RF) receiver signal correction. For RF receiver circuitry () having receive path and a warmup period associated therewith and including at least one analog baseband gain control stage () having a gain associated therewith, the method includes the step of performing a DC correction calculation operation during the warmup period to derive a DC correction value having a first component and a second component for each of the at least one gain control stage (). The DC correction calculation step includes the steps of performing a first closed loop correction () of a baseband path to derive the first component of the DC correction value and performing a second closed loop correction () of the receive path as a function of the () gain during the warmup period to derive the second component of the DC correction value. During operation after the warmup period (), an open loop correction is performed for instantaneous DC correction as function of the PMA () gain and the DC correction value.

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Vernon Hills, IL, United States of America

Manish N Shah