Ambarella, Inc.

Ambarella International LP

Manish K Singh

Dingxin Jin

Leslie D Kohn

An apparatus including a plurality of page circuits and a common request circuit. The page circuits may each be implemented within a respective memory bank controller of a memory bank set and store an address and determine a page hit status. The common request circuit may be implemented within the memory bank set and store client requests and issue a command corresponding to the client requests in response to the page hit status and an order of storage of the client requests. The page circuits may comprise half a storage depth of the common request circuit. The common request circuit may be shared between each of the memory bank controllers of the memory bank set. The memory bank controllers may control access to a random access memory. The address, the client requests and the page hit status may enable buffering to provide a preview of upcoming client requests.

Request buffering scheme

An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.

Hierarchical arbitration structure

An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to set a flag where a current value in a current line of an image is a maximum value in a first window in the current line. The second circuit may be configured to reset the flag based on one or more previous lines of the image where the current value is not a largest value in a second window around the current value. The third circuit may be configured to generate an output value as (i) the current value if the flag is set and (ii) a predetermined value if the flag is reset.

Non-maximum suppression in image data

An apparatus includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to (i) receive an image in a raster order, where the image has a plurality of data values arranged in a plurality of raster lines, and (ii) set a flag corresponding to a current value among the data values in a current line of the raster lines to indicate that the current value is a maximum value in a one-dimensional window in the current line. The second circuit may be configured to reset the flag based on one or more previous lines of the raster lines to indicate that the current value is not the maximum value in a two-dimensional window around the current value. The third circuit may be configured to generate an output value in the current line based on the flag.

An apparatus includes a first circuit and a second circuit. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying an original matrix by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between a row order and a column order. The second circuit may be configured to generate a given matrix by reading the intermediate matrices from the memory in a second order that alternates between the column order and the row order.

Two-dimensional transformation with minimum buffering

An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a sequence of intermediate matrices by multiplying a sequence of original matrices by a predetermined matrix and (ii) write the intermediate matrices into a memory in a first order that alternates between (a) a first of the intermediate matrices in a row order and (b) a second of the intermediate matrices in a column order. The second circuit may be configured to (i) read the sequence of the intermediate matrices from the memory in a second order that alternates between (a) the first intermediate matrix in the column order and (b) the second intermediate matrix in the row order and (ii) generate a sequence of transform matrices by multiplying the intermediate matrices as read from the memory by another predetermined matrix.

An apparatus including a memory, a first circuit and a second circuit. The memory may be divided into eight banks. Each bank may store a portion of a three-dimensional (3D) color correction lookup table. The first circuit may be configured to address the memory in response to an index of an input point. The second circuit may be configured to arrange outputs of the eight banks for color interpolation.

High performance memory system for 3D color correction

An apparatus generally having a first memory, a second memory and a circuit is disclosed. The first memory may be configured to store a warp table. The warp table is generally accessed through a single data port of the first memory. The second memory may be configured to buffer an input image. The input image may have a plurality of input pixels arranged in two dimensions. The circuit may be configured to generate an output image by a warp correction of an input image. The warp correction may be defined by the warp table. The output image may include a plurality of output pixels. At least one of the output pixels may be generated during each clock cycle of the circuit.

High performance warp correction in two-dimensional images

An apparatus generally having a first memory, a second memory and a circuit is disclosed. The first memory may be configured to store a warp table. The warp table is generally accessed through a single data port of the first memory. The second memory may be configured to buffer an input image. The input image may have a plurality of input pixels arranged in two dimensions. The circuit may be configured to generate an output image by a warp correction of an input image. The warp correction may be defined by the warp table. The output image may include a plurality of output pixels. At least one of the output pixels maybe generated during each clock cycle of the circuit.

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Mountain House, CA, United States of America

Manish K Singh