Texas Instruments Corporation

Samsung Electronics Co., Ltd.

Other

Texas Instruments Incorporated Deutschland, Gmbh

Manish Goel

Seok-Jun Lee

Yuming Zhu

Srinath Hosur

Michael Oliver Polley

Srinivas Lingam

David Patrick Magee

Clive D Bittlestone

Hun-Seok Kim

Johann Zipperer

Joyce Kwong

Jing-Fei Ren

Hugh Pryor McAdams

Akila Subramaniam

Michael Thomas DiRenzo

Kyong Ho Lee

Jose A Rodriguez-Latorre

Anand Ganesh Dabak

Anuj Batra

Jaiganesh Balakrishnan

Xiaolin Lu

Chenchi Luo

Muhammad Zubair Ikram

Sourabh Ravindran

Hideo Tamama

Rami Abdallah

Aris Papasakellariou

Eko Nugroho Onggosanusi

Timothy M Schmidl

Hamid Rahim Sheikh

Krishnaswamy Nagaraj

Srikanth Gummadi

David D Liu

Yang Sun

Hirohisa Yamaguchi

Donald Phillip Shaver

Sai Zhang

Michael T Direnzo

Dale E Hocevar

John Seokjun Lee

Yanni Chen

Assaf Sella

Yunchen Qiu

Mingoo Seok

Vitali Loseu

Xiao Pu

Branislav Kisacanin

Antonio F Mondragon-Torres

Nathan R Belk

Hyejung Kim

Siddharth K Advani

Ayush Goel

Steven P Pekarich

Rahul Rithe

Jeffrey Tang

Dongsuk Jeon

Eric P Kim

Angel Mary Lourdu

Michael D Direnzo

Kyong-Ho Lee

Jin Meng Ho

Micahel T Direnzo

Methods and apparatus for creating a physically unclonable function for SRAM are disclosed. An example method includes decreasing a supply voltage of a memory array to a first voltage level, the first voltage level being below a normal operating voltage associated with the memory array, reading a first value of a bit cell after the supply voltage has been at the first voltage level, and determining a function based on the first value of the bit cell and a second value, the second value stored in the bit cell when the memory array is operating at a voltage level above the first voltage level, the function to represent an identification of a circuit including the memory array.

Methods and apparatus to create a physically unclonable function

A method for providing authentication using an image sensor of an electronic device including: receiving, by the electronic device, a plurality of frames from the image sensor of the electronic device, wherein each frame includes a plurality of Optical Black (OB) pixels; determining, by the electronic device, a set of optimal OB pixels from the plurality of frames; and generating, by the electronic device, a unique key based on the set of optimal OB pixels for the authentication.

Method and electronic device for providing authentication using an image sensor

Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

Methods and apparatus to determine and apply polarity-based error correction code

A method, an electronic device, and computer readable medium are provided. The method includes receiving an input into a neural network that includes a kernel. The method also includes generating, during a convolution operation of the neural network, multiple panel matrices based on different portions of the input. The method additionally includes successively combining each of the multiple panel matrices with the kernel to generate an output. Generating the multiple panel matrices can include mapping elements within a moving window of the input onto columns of an indexing matrix, where a size of the window corresponds to the size of the kernel.

Convolution streaming engine for deep neural networks

An electronic device, method, and computer readable medium for 3D association of detected objects are provided. The electronic device includes a memory and at least one processor coupled to the memory. The at least one processor configured to convolve an input to a neural network with a basis kernel to generate a convolution result, scale the convolution result by a scalar to create a scaled convolution result, and combine the scaled convolution result with one or more of a plurality of scaled convolution results to generate an output feature map.

System and method for convolutional layer structure for neural networks

Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Low energy accelerator processor architecture with short parallel instruction word

In described examples, data are stored in a destructive read non-volatile memory (DRNVM). The DRNVM includes an array of DRNVM cells organized as rows of data. The rows of data are subdivided into columns of code word symbols. Each column of code word symbols is encoded to store an error correction code symbol for each column of code word symbols.

Methods and apparatus to detect and correct errors in destructive read non-volatile memory

A method of performing loop closure detection is described. The method comprises detecting a movement of a device having a camera; and adaptively disabling or enabling, using a processor of the device, a loop closure detection of the device based upon the detected movement of the device.

Performing a loop closure detection

A method of performing an iterative bundle adjustment for an imaging device is described. The method comprising implementing a plurality of functions in performing a bundle adjustment. Predetermined functions of the plurality of functions may be started using a processor for a second iteration in parallel with a first iteration of the plurality of functions. A result of the predetermined functions started during the first iteration may be used in a second iteration. An output of the bundle adjustment may then be generated for successive iterations.

Performing an iterative bundle adjustment for an imaging device

An electronic device, method, and computer readable medium for foveated storage and processing are provided. The electronic device includes a memory, and a processor coupled to the memory. The processor performs head tracking and eye tracking; generates a foveated image from an original image based on the head tracking and the eye tracking; and stores the foveated image using one of: a tile-based method or a frame-based method.

Foveated domain storage and processing

An electronic device, method, and computer readable medium for 3D association of detected objects are provided. The electronic device includes at least one image sensor, an inertial measurement sensor, a memory, and at least one processor coupled to the at least one image sensor, the inertial measurement sensor, and the memory. The at least one processor is configured to capture an image of an environment using the at least one image sensor, detect an object in the captured image, define a bounded area in the image around the detected object, receive head pose data from the inertial measurement sensor, and determine a location of the detected object in a 3D space using the head pose data and the bounded area in the captured image.

System and method for 3D association of detected objects

Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Methods and instructions for a 32-bit arithmetic support using 16-bit multiply and 32-bit addition

A method of implementing memory transfers for image warping in an electronic device is described. The method comprises receiving an input tile associated with an image; generating a geometric boundary around pixels of the input tile; and remapping the pixels in the geometric boundary to an output tile. An electronic device and a non-transitory computer readable storage medium for performing the method are also disclosed.

Electronic devices for and methods of implementing memory transfers for image warping in an electronic device

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Plano, TX, United States of America

Manish Goel