Qualcomm Incorporated

Manish Garg

Pratibind Kumar Jha

Santhosh Reddy Akavaram

Prakhar Srivastava

Ashwini Pandey

Abhishek Ghosh

Sridhar Anumala

Sonali Jabreva

Hung Vuong

Shiva Kumar Mangali

Sairam Varada

Shubham Kanwal

Reddy Vijay Gudi

Aspects relate to interrupting memory access during background operations of a memory device. In one example, a host for a memory device includes background operation circuitry configured to permit a background operation by a memory device. The host is coupled to the memory device through a bus. The host receives an operation completed notification from the memory device to indicate that the memory device has completed performing the background operation. Memory access command circuitry is configured to receive a memory access command. The memory access command concerns reading or writing data to the memory device coupled to the host. The memory access command circuitry initiates a wait at the host for the memory access command, and sends the memory access command to the memory device in response to receiving the operation completed notification.

Interrupting memory access during background operations on a memory device

In some aspects, a memory system may detect that a host device of the memory system has a low battery status using a comparison of a battery level of the host device to a low battery threshold. The memory system may set, in association with detecting that the host device has the low battery status, a low battery status indication of a status register for a memory device of the memory system to indicate that the host device has the low battery status. The memory system may cause, in association with the status register indicating the low battery status indication, one or more background operations of the memory device to be deferred or unexecuted. Numerous other aspects are described.

Memory device background operation management for low host battery

A host device includes system memory that includes a logical-to-physical (L2P) cache and a second cache. The host device also includes a host controller interface (HCI) configured to be coupled to a flash memory device. The HCI is configured to determine that a particular region of a L2P address mapping table is to be removed from the L2P cache. The L2P address mapping table is configured to include mappings between logical memory addresses and physical memory addresses of the flash memory device. The HCI is also configured to identify a particular sub-region of the particular region having an access metric that satisfies a retention criterion. The HCI is further configured to store the particular sub-region into the second cache. The HCI is also configured to remove the particular region from the L2P cache.

Host device caching of flash memory address mappings

Disclosed are systems and techniques for multiuser communications. For instance, a process can include establishing a multiuser call, the multiuser call including at least two other network devices. The process can further include receiving a request to record the multiuser call, receiving an indication to disable recording for a second network device, and causing recording of data from the second network device on the multiuser call to be disabled.

Selective recording of multiuser calls

Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.

System and method for updating memory tables

Methods that may be performed by a universal flash storage (UFS) device of a computing device for configuring flash memory cells. Various embodiments may include setting a number of degraded triple-level cells (TLCs) attribute, and configuring at least one degraded TLC as at least one single-level cell (SLC) based on the number of degraded TLCs attribute, the at least one degraded TLC being not functional as a TLC and functional as an SLC. Some embodiments may include identifying the at least one degraded TLC based on at least one degradation attribute associated with the at least one degraded TLC, the at least one degradation attribute configured to indicate that the at least one degraded TLC is not functional as a TLC, and identifying an amount of degraded TLCs that are not functional as a TLC.

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Hyderabad Telangana, India

Manish Garg