Nxp B.v.

Manish Garg

Andrei Sergeevich Terechko

Atul Katoch

Jose De Jesus Pineda De Gyvez

Evert Seevinck

Hendricus Joseph Maria Veendrick

Kiran Batni Raghavendra Rao

A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction.

Arrangement and method for controlling power modes of hardware resources

A method for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising, in an active state, providing a regular power supply (VDD) and a standby power supply (VDD STANDBY) to the state retaining circuit; for a transition from an active state to a standby state, decreasing the regular power supply to ground level and maintaining the standby power supply (VDD STANDBY) thus providing the circuit elements () of the state retaining circuit with enough power for retaining the state during standby mode; and for a transition from the standby state to the active state, increasing the regular power supply (VDD) from its ground level to its active level. A circuit for reducing the power consumption in a state retaining circuit during a standby mode is disclosed comprising a control unit () providing at least one control signal; a data input unit () providing at least one input signal; a data output unit () providing at least one output signal; a data storage unit () for holding the state of the circuit during an a standby mode; a regular power supply supplying power to the data storage unit () during an active mode; and a standby power supply supplying power to at least a part of the data storage unit () during the active mode and the standby mode.

Method for reducing power consumption in a state retaining circuit, state retaining circuit and electronic device

A circuit arrangement and method of controlling power dissipation utilize a register file () with power dissipation control capabilities through a banked register design coupled with enable logic () that is configured to selectively disable unused banks () of registers by selectively gating off clock (), address () and data () inputs supplied thereto.

Register file gating to reduce microprocessor power dissipation

A circuit arrangement, method of executing program code and method of generating program code utilize power control instructions () capable of dynamically controlling power dissipation of multiple hardware resources (-) during execution of a program by a processor (). Moreover, a processor () configured to process such power control instructions () is capable of maintaining the power modes of the multiple hardware resources (-) to that specified in an earlier-processed power control instruction (), such that subsequently-processed instructions (90) will be processed while the power modes of the multiple hardware resources (-) are set to that specified by the earlier-processed power control instruction ().

As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

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Eindhoven, Netherlands

Manish Garg