Samsung Electronics Co., Ltd.

General Electric Company

Microsoft Technology Licensing, LLC

Texas Instruments Corporation

Sap Se

Bl Technologies, Inc.

Manish Chandra Joshi

Parvinder Kumar Rana

Lava Kumar Pulluru

Jayaprakash Sandhala Radhakrishnan

Poornima Venkatasubramanian

Pushp Khatter

Ankur Gupta

Nimeshkumar Kantilal Patel

Vijaysai Prasad

Richard Stephen Hutte

Akash Kumar Gupta

Alagarsamy Subbiah

Muthukumar Nagu

Shibnath Mukherjee

Arjun Bhattacharyya

Abhishek Kesarwani

Sathees Kesavan

Ved Prakash

Rebika Mayanglambam Devi

Jeffrey Allen Zurlo

Rupam Basu

Gopi Sunanth Kumar Gogineni

Ashok Shankar Shetty

Robert Edward Deallenbach

Lakshmikantha V Holla

Santosh V

Gerd Moser

Romit Ghosh

Peter Roth

Santosh Kumar Addanki

Anurag Kumar

Puneet Suri

Siva Kumar Kota

Karthikeyan Loganathan

Vivekanandhan Thiruvettipuram Madhivanan

Dhaval Desai

Suvarna Kharidehal

Shubham Ranjan

Antony Raja T

Anomit Ghosh

Marina Wochner

Thomas Mocker

Janardhan Achanta

Steffen Schloenvoigt

Rajarajan Rathina

Glenn Vernon Kenreck, Jr

Surendra Deshmukh

Karthikeyan Somashekara

Ambuj Jain

Rhomit Ghosh

Jr Glenn Vernon Kenreck

A memory device, includes a voltage and temperature sensing circuit configured to generate a Pull Down (PD) signal that varies based on upon at least one of a voltage and temperature at the memory device; and primary pull down paths provided with secondary pull down paths, wherein the primary pull down paths are provided separately at a Dummy Read Bit line (DRBL) and a Dummy Global Read Bit line (DGRBL), wherein the secondary pull down paths are provided separately for the DRBL and the DGRBL parallel to the respective primary pull down paths. The voltage and temperature sensing circuit is configured to perform at least one of: controlling at least one of the secondary pull down paths based on a voltage of the PD signal; varying a discharge time of at least one of the dummy bit-lines based on the voltage of the PD signal; and generating an early reset signal at one of a high temperature condition and a high voltage condition based on the voltage of the PD signal.

Memory device including voltage and temperature sensing circuit and method for managing operation thereof

Various example embodiments of the inventive concepts include a SRAM apparatus including a left memory array and right memory array, each of the left memory array and the right memory array including a left memory array and a right memory array, each comprising a plurality of columns, the plurality of columns in each of the left memory array and the right memory array divided into a plurality of segments, and each of the segments comprising a plurality of memory bit cells, and central driver circuitry comprising a plurality of driver devices, each of the plurality of driver devices communicatively connected to a corresponding segment of the plurality of segments through a corresponding metal control line of a plurality of metal control lines, the central driver circuitry configured to route at least one array signal to at least one segment of the plurality of segments.

Static random-access memory (SRAM) apparatus and method for reducing wire delay

A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Write assist circuit for static random-access memory (SRAM)

A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

Methods and systems for managing read operation of memory device with single ended read path

The present invention discloses a wordline driver circuit for a random-access memory (RAM), which can reduce leakage during power down mode. The circuit includes a pre-driver stage on header and footer. The pre-driver stage includes a strap buffer defining a header and comprising a first switch connecting a first set of wordlines to a first voltage. The pre-driver stage includes an input-output buffer defining a footer and comprising a second switch connecting a second set of wordlines to a second voltage. In the pre-driver stage, the strap buffer further includes a third switch connecting the second set of wordlines to the first voltage and a fourth switch connecting the first set of wordlines to the second voltage.

Circuits for power down leakage reduction in random-access memory

Embodiments of the disclosure extract annotations from web pages. The annotations are combined with search results and/or advertisements to allow the user to better understand the content of the search result or advertisement landing web page. A visual snapshot of the web page is taken. Visual processing extracts information from the visual representation. The HTML, for the web page is also analyzed and various pieces of information extracted. The information from the visual processing is combined with the information extracted from the HTML. The combined information is evaluated and information for the annotations are selected. The annotations are then combined with the search results and/or advertisements.

Visual parsing for annotation extraction

Embodiments of the disclosure extract annotations from web pages. The annotations are combined with search results and/or advertisements to allow the user to better understand the content of the search result or advertisement landing web page. A visual snapshot of the web page is taken. Visual processing extracts information from the visual representation. The HTML for the web page is also analyzed and various pieces of information extracted. The information from the visual processing is combined with the information extracted from the HTML. The combined information is evaluated and information for the annotations are selected. The annotations are then combined with the search results and/or advertisements.

Embodiments herein provide a Static Random-Access Memory (SRAM) system with a delay tuning circuitry and a delay control circuitry and a method thereof. Delay tuning circuitry in the SRAM system may provide a tuning of reset time in the generation of an internal clock by introducing a delay. The delay is introduced according to a process state of periphery circuitry in the SRAM. A delay control circuitry provides a control over delay in reset time of the internal clock by varying a discharge rate for each of a Dummy Bit Line (DBL) circuitry and Complementary Bit Line Circuitry (CDBL), by connecting a stack of NMOS transistors over discharge NMOS transistors.

Static random-access memory (SRAM) system with delay tuning and control and a method thereof

Provided are apparatus and methods for compensating fabrication process variation of on-chip component(s) in shared memory bank. The method includes tracking a flip voltage level and tracking a discharge leakage current to disconnect a keeper circuit from the local read bit-line. The method includes controlling a read current and the discharge leakage current based on determining at least one of fast transistor and slow transistor associated with the at least one the keeper circuit and a bit-cell.

Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory

A fin-Field Effect Transistor based system on chip (SoC) memory is provided and includes a control block, first logic gates, and row decoder blocks. The control block includes a clock generator circuit that generates an internal clock signal, and a global driver circuit coupled to the clock generator circuit that drives a global clock signal. Each row decoder block includes a second logic gate that receives higher order non-clocked address signals via input terminals, a transmission gate that combines the global clock signal and the higher order non-clocked address signals, third logic gates that receive lower order non-clocked address signals and higher order clocked address signals, and output a combined lower order address and higher order address along with the global clock signal, level shifter circuits that receive the outputs, and word-line driver circuits that generate word-lines based on the output of the level shifter circuits.

Methods and systems for performing decoding in finFET based memories

The present invention concerns a method of providing advisory controls for a desalter system. The method allows a user to continuously monitor performance of the desalter system, to continuously monitor position of the emulsion band (or rag layer), to control the emulsion band using demulsifiers, and to recommend to users how to maintain optimal pressure drop at the mixing device of the desalter system. This is achieved by using a first principles based model combined with a sensor to measure the position, quality and size of the emulsion band. The first principles based model takes into account the geometry of the desalter system, physical properties of the crude oil and water, as well as the operating conditions. Thus, the method provides users with sensing of an emulsion layer through direct measurements and also gives recommendations on appropriate corrective actions to be initiated during upsets.

Advisory controls of desalter system

A memory for providing a signal buffering scheme for array and periphery signals and the operating method of the same are provided. The memory includes a plurality of columns of memory cells, a control circuit, and a control logic unit. The plurality of columns of memory cells may be connected to a local array signal generator via local control lines, which are connected to a global array signal generator via global control lines for receiving array signals. The control circuit may be connected to the memory cells for providing periphery signals. The control logic unit may be connected to the memory cells through a hierarchical structure of the global control lines and the local control lines. The control logic unit may be configured to provide the array signals and periphery signals having the same polarity to the global control lines and the local control lines.

Memory providing signal buffering scheme for array and periphery signals and operating method of the same

An injection quill design and methods of use for injecting a first fluid into a second fluid. The injection quill may comprise a hollow stem having a closed end and a sidewall, the stem having a curved cross-section defined by a major axis, and a minor axis, and at least one orifice for injecting the first fluid into the second fluid, wherein the major axis is greater than the minor axis and/or the orifice extends through the sidewall and/or the orifice has an internal chamfer with a chamfer angle ranging from less than 0&#xb0; but greater than 90&#xb0;.

Injection quill designs and methods of use

Treatment compositions for neutralizing acidic species and reducing hydrochloride and amine salts in a fluid hydrocarbon stream are disclosed. The treatment compositions may comprise at least one amine with a salt precipitation potential index of equal to or less than about 1.0. Methods for neutralizing acidic species and reducing deposits of hydrochloride and amine salts in a hydrocarbon refining process are also disclosed. The methods may comprise providing a fluid hydrocarbon stream and adding a treatment composition to the fluid hydrocarbon stream. The treatment compositions used may have a salt precipitation potential index of equal to or less than about 1.0 and comprise either water-soluble or oil-soluble amines.

Compounds and methods for inhibiting corrosion in hydrocarbon processing units

A system on-chip (SoC) device is provided. The SoC device includes an on-chip memory including memory banks, and internal clock generators. Each internal clock generator is coupled to one or more memory banks. Each internal clock generator generates one or more of an internal clock signal, a control signal and a clock reset signal locally for the memory bank to which the internal clock generator is coupled.

System on-chip (SoC) device with dedicated clock generator for memory banks

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Bengaluru, India

Manish Chandra Joshi