Cadence Design Systems, Inc.

Manish Bhatia

Sourav Kumar Sircar

Marc Heyberger

Akash Khandelwal

Lalit Bharat

Chunlong Pan

Ruchir Agarwal

Anurag Saran

Namrata M Sadhankar

Renuka Deshpande

Alwin Gupta

Disclosed are methods, systems, and articles of manufacture for implementing electronic design closure with reduction techniques. A timing graph and compact timing data for an analysis view of a set of analysis views may be determined for an electronic design. A reduced set of dominant analysis views may be determined based at least in part upon a result of a timing dominance analysis. Timing data may be loaded for at least the reduced set of dominant analysis views; and a design closure task may be performed on the electronic design using at least the timing data and the reduced set of dominance analysis views.

Method, system, and computer program product for implementing electronic design closure with reduction techniques

Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.

Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure

Growing community of inventors

Ghaziabad, India

Manish Bhatia