Cadence Design Systems, Inc.

Manish Bansal

Naresh Kumar

Prashant Sethia

Umesh Gupta

Rakesh Agarwal

Manuj Verma

Vishnu Kumar

Ajay Tomar

Kaustav Guha

Sourabh Kumar Verma

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis ('GBA') violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis ('PBA') on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Comprehensive path based analysis process

Methods and systems provide setup and generation of SPICE results for a set of timing path(s) and integration of SPICE simulation with static timing analysis (STA) path-based results generation. In an embodiment, a method may select a candidate set of timing paths, perform path based analysis (PBA) on the selected paths, generate SPICE results for the selected paths, and render the PBA and SPICE results in an integrated user interface to facilitate sign off based on annotated constraints and correlation between STA results and SPICE results. Methods and systems of the present disclosure find application in, among other things, timing signoff in an electronic design and verification process.

Method and apparatus for integrating spice-based timing using sign-off path-based analysis

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Delhi, India

Manish Bansal