Dxcorr Design Inc.

Manish Agarwal

Rajesh Tiruvuru

Nirmalya Ghosh

An electronic biasing circuit for memory operating in a high temperature environment, comprising a first memory cell and a second memory cell, a first MOSFET transistor electrically coupled in series with the first memory cell, wherein the first MOSFET transistor is configured as a switch, a second MOSFET transistor electrically coupled in series with the second memory cell, wherein the second MOSFET transistor is configured as a switch, a DC bias current source configured to generate a negative DC bias voltage signal, a first read/word line electrically coupled to a gate of the first MOSFET transistor, and a second read/word line electrically coupled to a gate of the second MOSFET transistor, wherein in response to a read operation of the first memory cell, the second read/word line is configured to deliver the negative DC bias voltage signal to the gate of the second MOSFET transistor.

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Fagu, India

Manish Agarwal