Oracle International Corporation

Mani Viswanath

Thomas Mitchell

John Eitrheim

A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells assigned to a plurality of cell groups. The method may further include obtaining, from a user, a selection of a user-defined criterion and a selected cell group from the plurality of cell groups. The method may further include partitioning the selected cell group into a first partitioned cell group including a first subset of the plurality of cells and a second partitioned cell group comprising a second subset of the plurality of cells. The method may further include generating a floorplan comprising the first partitioned cell group and the second partitioned cell group.

User-defined partitions for logical and physical circuit syntheses

A method for designing a circuit. The method may include obtaining a register-transfer level (RTL) file for an integrated circuit. The method may further include generating, using an RTL-Synthesis compiler and from the RTL file, a gate-level netlist including a plurality of cells for the integrated circuit. The method may further include determining, using a cross-probe criterion, an amount of cross-correlation between a first cell and a second cell in the gate-level netlist. The method may further include generating, in response to the amount of cross-correlation exceeding a correlation threshold, a cell group including the first cell and the second cell. The method may further include determining a boundary condition for the cell group. The method may further include generating a floorplan. The first cell and the second cell may be placed in the floorplan according to the boundary condition.

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Austin, TX, United States of America

Mani Viswanath