Adv Antest Corporation

Other

University of Washington

Mani Soma

Takahiro Yamaguchi

Masahiro Ishida

Toshifumi Watanabe

Kiyotaka Ichiyama

Yasuo Furukawa

Masayoshi Ichikawa

Minako Yoshida

Hirobumi Musha

Masayuki Kawabata

Yasuhiro Maeda

Welela Haileselassie

George A Barrett

Jessica Yan

Seongwon Kim

Douglas S Ramsay

Chris Prall

A jitter measuring apparatus measures timing jitter of a signal-under-test. The jitter measuring apparatus includes a pulse generator for outputting a pulse signal of a predetermined pulse width for an edge of the signal-under-test, and a jitter measuring sub-unit for extracting the timing jitter on the basis of a duty ratio of each cycle of the signal output by the pulse generator.

Jitter measurement apparatus, jitter measurement method, test apparatus and electronic device

There is provided a measuring apparatus for measuring a signal-to-noise ratio of a discrete waveform which is output from an AD converter in response to an input signal, where the signal-to-noise ratio indicates a ratio of a signal component of the input signal to noise generated by the AD converter. The measuring apparatus includes a spectrum compensating section that receives a spectrum of the discrete waveform output from the AD converter, and compensates the received spectrum in accordance with a non-symmetric sideband between an upper sideband and a lower sideband of the received spectrum, where the upper and lower sidebands are defined with respect to a fundamental frequency of the input signal, and a phase noise waveform calculating section that calculates a phase noise waveform of the discrete waveform based on the spectrum which has been compensated by the spectrum compensating section.

Signal-to-noise ratio measurement for discrete waveform

A measuring apparatus including a timing jitter estimator which estimates an output timing jitter sequence which indicates the output timing jitter of an output signal based on an output signal output from a DUT in response to an input signal input to the DUT, and a jitter transfer function estimator which estimates a jitter transfer function in the DUT based on the output timing jitter sequence. The jitter transfer function estimator includes an instantaneous phase noise estimator which estimates an instant phase noise of the output signal based on an output signal, and a resampler which generates the output timing jitter sequence by resampling the instantaneous phase noise at predetermined timing.

Measuring apparatus and measuring method

There is provided a clock generator for generating a single-phase clock into which jitter has been injected, having a multi-phase clock generating section for generating a plurality of clock signals having an almost equal phase difference from each other and a jitter injecting section for injecting jitter into the respective clock signals.

Test apparatus, clock generator and electronic device

A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.

Jitter measuring apparatus, jitter measuring method and PLL circuit

There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, including a pulse generating section having first pulse generating means for detecting edges of the data-signal-under-measurement to output a first pulse signal having a pulse width set in advance corresponding to the edge and second pulse generating means for detecting boundaries of data sections where data values do not change in the data-signal-under-measurement to output a second pulse signal having a pulse width set in advance over the edge timings of the boundaries of the detected data sections and a jitter calculating section for calculating timing jitter in the data-signal-under-measurement based on the first and second pulse signals.

Apparatus for measuring jitter and method of measuring jitter

There is provided a jitter measuring apparatus for measuring jitter in a signal-under-measurement, having a signal converting section for calculating a spectrum of the signal-under-measurement, a bandwidth calculating section for calculating frequency where a saturation rate of a value of the integrated spectrum of the signal-under-measurement becomes almost equal to a saturation rate set in advance in a band-to-be-measured set in advance as upper cutoff frequency of the band-to-be-measured to calculate the jitter and a jitter calculating section for measuring the jitter in the signal-under-measurement based on the spectaum in the band-to-be-measured of the signal-under-measurement.

A testing device for testing an electronic device is provided. The testing device includes: a deterministic jitter application unit for applying deterministic jitter to a given input signal without causing an amplitude modulation component and supplying the input signal with the deterministic jitter to the electronic device; a jitter amount controller for controlling the magnitude of the deterministic jitter generated by the deterministic jitter application unit; and a determination unit for determining whether or not the electronic device is defective based on an output signal output from the electronic device in accordance with the input signal.

Testing device for testing electronic device and testing method thereof

Timing jitter sequences &#x394;&#x3c6;[n] and &#x394;&#x3c6;[n] of respective clock signals under measurement x(t) and x(t) are estimated, and a timing difference sequence between those timing jitter sequences is calculated. In addition, initial phase angles &#x3c6;and &#x3c6;of linear instantaneous phases of the x(t) and x(t) are estimated, respectively. A sum of a difference between those initial angles and the timing difference sequence is calculated to obtain a clock skew sequence between the x(t) and x(t).

Apparatus for and method of measuring clock skew

Embodiments of the present invention apply wavelets to radio frequency (RF) signals to extract specific characteristics (e.g., jitter, phase variations, frequency variations) so that their timing, phase, and frequency components can be characterized. In one embodiment of the present invention, a Haar wavelet is used to extract timing characteristics. In another embodiment, a Morlet wavelet is used to extract phase characteristics. In still another embodiment, a Morlet wavelet is used to extract frequency characteristics.

Characterization of radio frequency (RF) signals using wavelet-based parameter extraction

A wideband signal analyzing apparatus for analyzing an input signal includes frequency-shifting means for generating a plurality of intermediate frequency signals by shifting a frequency of the input signal as much as respectively different frequency-shifting amounts, so that if a frequency band of the input signal is divided into a plurality of frequency bands, each of the frequency bands can be shifted to a predetermined intermediate band, spectrum measuring means for outputting a complex spectrum of each of the intermediate frequency signals, and spectrum reconstructing means for merging the complex spectra.

Wideband signal analyzing apparatus, wideband period jitter analyzing apparatus, and wideband skew analyzing apparatus

A testing apparatus for testing a device under test (DUT) includes a performance board; a main frame for generating a test signal for testing the DUT and determining pass/fail of the DUT based on an output signal output by the DUT; a pin electronics between the main frame and the performance board and performs sending and receiving signals between the main frame and the DUT; a deterministic jitter injecting unit for receiving the output signal without passing through the pin electronics and inputting a loop signal, which is the received output signal into which a deterministic jitter is injected, to an input pin of the DUT without passing through the pin electronics; and a switching unit for determining whether the input pin of the DUT is provided with the test signal output by the pin electronics or the loop signal output by the deterministic jitter injecting unit.

Test apparatus and test method for testing a device under test

A measuring apparatus for measuring reliability against jitter of an electronic device, including: a jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device based on an output signal output from the electronic device according to an input signal input through a transmission line of which the transmission length is shorter than a predetermined length so that it does not generate a deterministic jitter; a jitter tolerance degradation quantity estimator operable to estimate a quantity of degradation of the jitter tolerance which deteriorates by the deterministic jitter caused in the input signal by transmission through the long transmission line when the input signal is input into the electronic device through the transmission line, of which the transmission length is longer than a predetermined length so that it may cause the deterministic jitter; a system jitter tolerance estimator operable to estimate a jitter tolerance of the electronic device and a jitter tolerance of a system including the long transmission line and the electronic device based on quantity of degradation of the jitter tolerance, is provided.

Measurement instrument and measurement method

A probability estimating apparatus and method for peak-to-peak clock skews for testing the clock skews among a plurality of clock signals distributed by a clock distributing circuit, and for estimating the generation probability of the peak-to-peak value or peak value of the clock skews. The probability estimating apparatus for peak-to-peak values in clock skews includes a clock skew estimator for estimating clock skew sequences among the plurality of clock signals under test and a probability estimator for determining a generation probability of the peak-to-peak values in the clock skews among the plurality of clock signals under test based on the clock skew sequences from the clock skew estimator by applying Rayleigh distribution. The generation probability of the peak-to-peak value is estimated based on RMS values of the clock signals and the Rayleigh distribution.

Probability estimating apparatus and method for peak-to-peak clock skews

An electronic device having a semiconductor circuit formed therein includes a semiconductor device in which the semiconductor circuit is formed; and a light emitting device, formed integrally with the semiconductor device, for emitting light indicating a reference position of the semiconductor device.

Growing community of inventors

Seattle, WA, United States of America

Mani Soma