Micron Technology Incorporated

Mani Raghavendra Aravapalli

Rakeshkumar Dayabhai Vaghasiya

Dhruv Chauhan

Nicola Colella

Sridhar Prudviraj Gunda

Ritesh Tiwari

Anil Sindhi

Anilkumar Rameshbhai Sindhi

Methods, systems, and devices for overlay code retrieval from a host system are described. A memory system may determine that a set of code for execution by a processor of the memory system is absent from an executable memory of the processor. The memory system may prevent the processor from retrieving the set of code from a non-volatile memory of the memory system based on the set of code being designated for retrieval from a host system. The memory system may retrieve the set of code from a memory of a host system, instead of retrieving the set of code from the non-volatile memory, based on the set of code being designated for retrieval from the host system.

Overlay code retrieval from a host system

Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.

Zone write operation techniques

Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level. A relocation associated with refraining from relocating invalid data may be selected for relatively less-fragmented data, which may support increasing available space by relocating data to a physical block with available portions that may be written to, taking advantage of a relatively lower latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a less-granular level.

Data relocation scheme selection for a memory system

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Hyderabad Telangana, India

Mani Raghavendra Aravapalli